LabVIEW FPGA

[Vhdl.eu]

Hi all,

has anyone tried or fixed it to get the VHDL code that is generated by the
LabVIEW FPGA module?

I want to see what LabVIEW is generating (the VHDL code) before it is
sending this material to the Xilinx Compiler

Kind regards,
http://www.vhdl.eu

[Stuart_R]

Hi,

When compiling the LabVIEW code for use on the FPGA device, intermediate files are created first and these files are the VHDL that has been created from the VI. This is then fed into the Xilinx compiler. There is no way to see the VHDL code that is created from the VIs and this is not likely to be something that will ever be available to users for many reasons.

Thanks,

Stuart