LabVIEW FPGA Idea Exchange

[adalyn]

Coming to LabVIEW FPGA from a VHDL background I have found the language quite limiting, below I've listed the main issues I've found so far hoping that some of the other LabVIEW users can give tips on workarounds or NI can give an indication if they are going to support these in the future.

1. Limited support for constants

* Non-synthesisable math functions unavailiable to operate on constants (eg log2(x))

* Functions with constant only inputs are seen to have variable outputs to the LabVIEW error checker, eg indexing an array with the output of 1+1 will cause an unconstrained array error.

* SubVI controls cannot be defined as constants, thus for example, using a control to index an array will also cause an unconstrained array error.

VHDL includes several non-synthesizable functions in the ieee.math_real library (amongst others).  Complex user functions can be written that are interpreted at compile time to generate constants such as LUT values.

EG, the following can be used to find the number of bits required to represent a given unsigned number.

function bits(arg:NATURAL) return NATURAL is

begin

    return INTEGER(ceil(log2(real(arg))));

end bits;

2. No parallel loops on FPGA target VIs

I was particularly surprised by the inability to declare parallel instances of the same function without copy/paste N-times.  What seems natural to me in LabVIEW is to declare a parallel loop with N and P connected to the same constant, then so long as there are no data dependencies between iterations it should work.  Parallel loops are unsupported in LabVIEW FPGA, where they would be very beneficial.

In VHDL the Generate construct is almost an exact match the LabVIEW parallel loop.

parallel_counter: for i in clear'range generate

process(clk, reset)

variable count : unsigned(output(i)'range);

begin

if reset='1' then 

count := (others<='0');

elsif rising_edge(clk) then

if clear(i) = '1' then

count := (others<='0');

else

count := count + 1;

end if;

end if;

output(i) <= count;

end process;

end generate;

3. No support for arrays >1D

VHDL supports ND arrays of bits however LabVIEW FPGA only supports operations on 1D arrays.

--  unconstrained 2d vector type

--  unconstrained 2d vector type in VHDL

type std_logic_2d is array(integer range <>, integer range <>) of STD_LOGIC;

If anyone has tips on getting the most out of LabVIEW FPGA feel free to share.  If you have come across more functionality that is impossible in LabVIEW FPGA vs VHDL I'd also like to know.

Thanks,

-Adam

[muks]

LabVIEW FPGA Idea Exchange

You can suggest new features here

[adalyn]

@muks wrote:

LabVIEW FPGA Idea Exchange

You can suggest new features here

---

Thanks for the link, exactly what I was looking for.  The issues I've raised haven't been brought up there so I'll recreate this post in the form of a couple new "Ideas".

Thanks again.

-Adam

[Greg_J]

Hi adalyn,

You might also try creating a product suggestion, as that goes directly to NI R&D.

Thanks!

- Greg J

[Nagaa]

Hello every one i am a clad certified engineer i want to enter into fpga .  so should proceed with labview fpga tool kit or its better to learn vhdl language to implementing applications in fpga 

thank you

[crossrulz]

---

@Nagaa wrote:

Hello every one i am a clad certified engineer i want to enter into fpga .  so should proceed with labview fpga tool kit or its better to learn vhdl language to implementing applications in fpga 

thank you

---

That really depends on what you are trying to do.  If you are trying to program an NI RIO card/board, then you need to learn LV FPGA.  If you are trying to program an FPGA on its own, you are going to have to go the VHDL route.

[Nagaa]

Thank you crossrulz

With the help of labview fpga s.w can we program any other hardware other than ni hardware

[BillMe]

I think LabVIEW FPGA was developed from the point of view of enabling existing LV programmers to extend their programming abilities down into hardware. It made much more sense to make a working subset of LV functionality an abstraction of the equivalent VHDL.

By the way, it would be interesting to know if the VHDL code you posted would work if you placed it in a VHDL Node. That would possibly get you around some of the limitations you noted with LV FPGA itself.