LabVIEW FPGA and VHDL/Verilog code

[pawel]

Hello

What is the intermediate code generated by the LabVIEW FPGA toolkit. Is it VHDL or Verilog and is it possible to access it somehow.

Other question is: is it possible to use already written VHDL or Verilog code. If so, which one.

And finally, which one of VHDL or Verilog is more useful in conjunction with LabVIEW FPGA toolkit?

thanks in advance.

Pawel

[Meister]

Hi Pawel,

The code generated by the FPGA toolkit is VHDL and it is not possible to see this code.

It is easy to reuse already written VHDL code into your LabVIEW FPGA program using the HDL Interface Node. You can type your VHDL code directly into the node, and you can also specify .vhd files.

Verilog support as of now is not supported by the FPGA module.

Hope this answers your questions.

Regards

Meister

NIDK

[pawel]

Hi Meister

That clarifies my concerns in 100%.

Thanks a lot

cheers

Pawel

[m3nth]

Why would they want to let you see the VHDL code that gets generated--that wouldn't be any fun 🙂  ...takes all the magic out of it, and magic after all, is what sells 🙂

[rolfk]

Well, the files generated by LabVIEW FPGA are really just in some ways encrypted. No idea how exactly but I'm sure it is a standard feature of the Xilinx tool chain to provide encrypted or maybe even just obfuscated vhdl files to it to prevent IP theft.
I only hope that this encryption is not the reason the Xilinx tool chain is such a huge and slow beast in comparison to LabVIEW. After all what it does can't be that more complicated than what LabVIEW does, but it for sure is magnitudes slower 😉

Rolf Kalbermatter

[Oli_Wachno]

Having worked with XILINX tools a few years ago, I think NI is not the one to blame (this time ;-); those tools always have been

quite difficult to use and slooooooooooooooow, so why change.... ;-))

In my opinion, even if they gave you access to the generated VHDL code, it would definitely not be to easy to read; the same thing with every automatic code generation. Although I have to admit, that I'm quite curious about the implementation of some components, especially BlockRAM....

In my last design, I did all the low-level-highspeed parts using VHDL and integrated them into a HDL node within a SCTL. Worked fine that far. If I find the time, I'll try to rebuild at least parts of this design in LabVIEW to find out how effective the compiler works....

Oli

[pawel]

Hi Oli

But you are still only limmited to NI FGPA, right?

What would be interesting is to use LabVIEW to generate a code for any FPGA. That would so much decreat the development time (not optimization), and crack down some blind routes we often follow. So this is the only reason why it would be nice to have an access to VHDL.

On the other hand, if it is like rofl is saying, the code is intentionaly made unreadible, there will be very difficult to make use of it anyways.

cheers

Pawel

[Oli_Wachno]

Hi Pawel,

sorry for answering so late, I enjoyed a few days of holidays, so Happy New Year first of all 🙂

Right now, I'm limited to NI FPGA and some freeware-VHDL tools, that are available on the net, which is ok for me right now.

It's a nice idea, to use LabVIEW FPGA code for other hardware as well, but:

- the VHDL code produced by the FPGA module will be written in an optimized way to suit XILINX VIRTEX devices and using XILINX's library components. Thus trying to use the VHDL will still limit you to the XILINX FPGA family used... even more: the XILINX tool's timing analysis depends on the speed grade of the chip that's used, as well as the exact type... I haven't found a possibilty to change the compiler settings ..... furthermore you need to know the locations of the IO Pins.....

- Having said the above, I don't have to mention, that there is very little chance to use your VHDL code on other FPGA brands.....

So, as long as NI does not release a kind of "prototyping-FPGA" hardware with detailed description (which would be a nice ideas anyway ;-), no chance 😞 At least none, that I can see.

Or did I misunderstand you?

Cheers

Oli

[pawel]

Hi Oli

And a happy New Year to you too :).

I did not really expect the answer in this thread, it was a while ago when I posted it.

You are right that it would be great to have a genetic development FPGA to play with.

When I mentioned the use of LabVIEW to create a code, I did not really mean the development of the "suit" of the code, which interfaces to the pins etc. I was more thinking about useing LabVIEW for algorithms generation. But you are propably right that it will be limitted to the one supplier like Xilinx (which is not a bad solution for me anyways).

take care

Pawel

[subdew]

Meister,

You have stated that it is easy to reuse already written VHDL code by either typing the code in or by specifying external ".vhd" files.  If that's the case, I'm not referencing the correct information.

I have already read the application notes "Importing HDL Code into FPGA VIs Using the HDL Interface node" and "Integrating a Model from Xilinx SystemGenerator for DSP into LabVIEW FPGA".

After reading these two application notes, it seems that there are three primary methods to get existing VHDL code imported:

1)  by typing it in

2)  by using external ".vhd" files

3)  by importing a Xilinx netlist (still using external files)

I certainly don't want to retype all the code I would like to import.  It is also my understanding that when typing it in the I/Os are defined under the "parameter" tab and the VHDL goes in under the "code" tab.  This results in the "entity" being defined by the LabVIEW FPGA software and the user is unable to edit it.  Therefore if there were generics defined in the original entity, they are lost.

I have attempted using the "external file" tab to import the VHDL code as written, but for some reason I can't seem to get the LabVIEW FPGA module to recognize my external file.  The application note provides very little detail on importing external files.

I like the idea of importing a Xilinx netlist for several reasons:

1)  site license available at desktop for ModelSim, Synplicity & Xilinx ISE

2)  tools outside of the LabVIEW environment are much faster and have better optimization capabilities

3)  capability to have multiple developers working in the desktop environment

4)  massive on site library of existing VHDL code developed with a methodology that promotes "reuse"

What I don't like about importing a netlist, (unless I'm misunderstanding something) is that the "entity" now becomes a "component".  Therefore signal coding must be added to the "architecture" to connect the "component".

What I'm really looking for is some advice with regard to which method is the best approach and possibly a document that goes through the process step by step.

Can you provide some advice in this area and is there any such document that goes through the process step by step for the preferred method?

Assistance needed,

subdew