LabVIEW FPGA - Xilinx memory error

[WillD]

Currently I am compiling to the 1M gate, Virtex2, target.

I am pretty sure this FPGA is overmapped, but would like to know if it would fit on the 3M gate one, or at least see how far off I am.

The link regarding the /3GB switch says that under WinXP64 xst.exe can address the full 4GB allowed by 32bits.

[CarlaU]

Hi WillD,

There could be a few different issues going on here. Is their any possibility that you could post the code so that I can reproduce the problem over here? Also, can you post the error log files as well? Having both of these things would really help figure out why you are getting this Portability error. Thanks!

Carla

[RonW]

I'll just add my name to the roster of those with ERROR:Portability:3 problems. In my case it happens almost exactly 20 minutes into the compile. I'm using LV 8.5 under WinXP with 2GB RAM. I've got only three modules: a 9485 output module, a 9853 CAN interface, and a 9802 SD Card controller. I've also got large target-to-host, host-to-target, and target-scoped FIFOs, and a 1024-element array.

I'll experiment with disabling that stuff and see what happens.

[Mr._Jim]

I've been watching this thread for a while, trying to think of any advice.  If it's any help, here are some steps I took to keep dodging the problem:

1.    I actually increased my physical memory to 4 GB, which gave me quite a bit more breathing room before I got the error.  Even though 32 bit Windows doesn't recognize some of the memory, it does recognize most of it.

2.    My experience with the /3GB flag at bootup was hit or miss - sometimes it seemed to help, sometimes it didn't help at all.  Even with 4 Gigs of memory, I still occasionally hit the error, and sometimes I used the 3GB flag with success.  (Or maybe it was something else?  There are a lot of variables that contribute to the problem/success)

3.   Close every other program that you possibly can.  Also try tweaking the "performance" settings under the "Advanced" tab of your system properties.  (Right click My Computer and select properties)  Try to see if you can use another machine during compilation, or run your compilations overnight.  (I did the latter)

4.   Sacrifice a little speed in your application for simpler code.  In my case, I had a few instances of a reentrant calculation that I was using throughout the FPGA code.  Making only one instance of the calculation slowed down my loop a bit, but it bought me more time before I ran into both the overmapping error and the memory error.

It's really hard to say what actually helps, but a combination of these steps seemed to work for me.  I sincerely hope this helps you folks and that I've alleviated at least some of the frustration.

Good luck...

Jim

[CarlaU]

Hi RonW,

Just like I wrote earlier, there could be a few different things going on here. This error sometimes occurs due to resource overmapping but the only way to fully determine this would be to see the error log files and, if possible, the code that is producing these errors. If you could post both of those things then we can figure out what is going on and why you are getting this Portability error.

Carla

[EdH]

I have been developing an application using the R-7813 PCI. This board was chosen after some initial experiments indicated that the usage of the FPGA (as measured by SLICES in the compile server report) might exceed the space available in the R-7811 PCI board. The R7813 has nearly three times the space available (as measured in SLICES) versus the R-7811 board. The development environment is WinXP Professional, 4 GBytes of ram, dual core 3 GHz processor.

I have begun to run into the "infamous" Xilinx memory error as my FPGA design SLICE use approaches 4500 SLICES (well under the R-7813 capability of ~14000 SLICES). It occurred to me that there may be some method that has been developed to reduce the FPGA compile server memory use.

I tried the suggested "/3GB" switch for WinXP and the results were disappointing.

At present, it seems that I can not use the extra capability provided by the R-7813 board.

Are there any software switches, setup options, etc. that can affect the FPGA compile server memory usage? Are there specific archetectural choices in the FPGA elements (READ/WRITE, Methods) that cause changes in the compile server memory usage? For example, I have  discovered that using PORTS versus using individual I/O lines is apparently more efficient. LOOPS such as WHILE, FOR and single-cycle loops (when appropriate and valid) also seem to reduce the compile server memory usage.

[Charlie_P]

Good Afternoon EdH,

There are no tweaks that I am aware of in the compile server to boost its performance other than telling Windows to give that process a higher priority on the processor.  This will not fix memory issues, only processing time.

If available, a possible solution is to install LabVIEW on a Windows XP 64-bit system so that the OS can address more RAM; this will not necessarily give more RAM to LabVIEW or the compiler.  It will simply allow Windows to use the RAM that LabVIEW (and possibly the compiler) can not access, allowing for better maximization of RAM usage.

Taking into account some of the information in the following links about different aspects of FPGA efficiency, you may be able to reduce the code size.  This, is most likely not a fix, but good practice.

FPGA resource efficiency questions

     http://forums.ni.com/ni/board/message?board.id=170&message.id=276759&requireLogin=False

How Can I Optimize/Reduce FPGA Resource Usage?

     http://digital.ni.com/public.nsf/allkb/311C18E2D635FA338625714700664816?OpenDocumen

System Memory Requirements for Compiling LabVIEW FPGA Applications

     http://digital.ni.com/public.nsf/allkb/F89C3D88819B8DE68625744800815537?OpenDocument

[EdH]

Thank you.

[noli]

Is this thread still open?  I'm getting this error now, and the program to free up ram isn't working for me.   The thing is, I'm on a Vista 64-bit system with 8GB Ram, and it seems to bug out after using 4GB.   I am trying to compile a pretty big statechart on the FPGA, so that's not helping, but we have the PXI-7853R so there's plenty of space on the device.  Any help (working solutions) would be apprieciated.

Thanks

[noli]

Here is my xflow log from the compilation