LabVIEW FPGA: Spurious interrupt using Interrupt VI

[BillMe]

FPGA VI:
While loop waiting for the rising edge of a pulse. Once detected, the pulse width is measured. Once the pulse width is determined, the FPGA VI generates an IRQ and waits to be cleared.

HOST VI:
Waits for an IRQ from the FPGA. When detected, the pulse width indicator on the FPGA is read and the IRQ is acknowledged.

FPGA VI:
Once the IRQ is cleared, the while loop repeats by waiting for a rising edge. There is no second pulse.

HOST VI:
When the host VI is run again and Waits for an IRQ, the same number interrupt is immediately detected. The interrupt is acknowledged and the pulse width read, in this case it's value is 0xFFFF (meaning the FPGA while loop start and end counts were equal).

QUESTION:
Why when running the host VI a second time is there still an interrupt pending? And why does it work when a small delay is introduced in the host VI between the reading of the pulse width indicator and acknowledging the interrupt??


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Message Edited by Bill@NGC on 11-15-2007 10:14 PM

[Erik_J]

Good morning Bill,

I understand that you talked with a NI Applications Engineer regarding this issue and it seems that the problem may be due to the RIU Pulse Width and Inturrupt not being serialized.  Please let us know the result of serializing the Inturrupt and RIU Pulse Width so we can update this thread for the community.

Thank you Bill!

Regards,
Erik J.
Applications Engineer
National Instruments