LabVIEW FPGA (Non-SCTL) Latency Estimates without Hardware

[tcapuano-aps]

Hey All,

I am trying to gather some benchmarks for different LabVIEW FPGA implements of the same function. For example, both of these sequences should implement the same behavior, but I don't know if LabVIEW FPGA is capable of understanding that this shouldn't do anything other than rewire some numbers on the FPGA. This is why I need the benchmarks.

To me, it seems like I should be able to use Xilinx Simulation to get an idea this latency. I can't find any up to date information on how to run this tool. LabVIEW Simulation says 0 cycles for both implementations, due to the lack of delay for math/logic. It seems like the only method to get this metric is to compile a bitfile and deploy it. I am hoping that I am wrong...

Thanks,

Tom