LabVIEW FPGA FIFOs

[IhmeKyselijä]

Hi,

I'm asking a stupid question just to check if I am stupid 🙂

So I am using a premade example code to do the target to host streaming (Example Finder -> Hardware input and output -> Integrated IO -> Getting started) My target is a PXIe-5774.

Here is the code that sends data to the host pc:

My question is that of the DRAM-FIFO and Target to host FIFO sizes. As I understand, the DRAM-FIFO size is 67108864 bits(?) which means I can store up to 4194304  16 bit values in there. On the other hand, the Target to host FIFO size is 65535 16 bit intergers. When my code finishes I want to send 327680 16 bit values to the host. 

1. Does that mean that the FIFOs are going to fill up?

2. When they fill up does the "Ready for input value assert False to tell the D-FIFO that it can't send any more data?

3. And if so, Can the DRAM-FIFO store enough data so that none get lost?

I don't want some of my data to get lost on the stream. If there is going to be data loss, how can I prevent it? I tried to increase the Target- to-host FIFO size but I ran out of block RAM.

Thanks:

Aarni

[Terry_ALE · Accepted solution]

Your capture size is smaller than the buffers so I think you should be fine.  You can test this with a known signal to confirm.