LabVIEW FPGA Can't Write Input to text file

[Moris]

Hi Thomas,

I want to save it on PC host. But I guess this code is just saving it on RT host. Should I use FIFO or is there simpler way to do that?

Thanks for the help,

Moris

P.S: I am now looking at this tutorial to learn about FIFO http://zone.ni.com/devzone/cda/tut/p/id/4534

[trouinky]

FIFO is great, we'll get to that shortly.  How fast are you needing to sample, i.e. how fast do you plan to make the DAQ loop turn on the FPGA?  Do you need to stream the data to a file (that gets larger and larger as you go along) or do you plan to do a capture of data for some fixed amount of time?  The file saving step will be trivial once we answer these questions...

[Moris]

Thomas: "How fast are you needing to sample?" Moris: I do not have the answer for this yet, I need to find out about sampling rate. I would like to make it as fast as possible without modelling the noise. Maybe hundreds of KHz?! Do you know how I can decide about the sampling rate? Frem theroy, I know that I am supposed to look at the bandwidth of the input and output commands and choosing a proper sampling rate keeping nyquist and aliasing in mind. Do you need to stream the data to a file (that gets larger and larger as you go along)?  Yes, I need to stream the data to a file to make further analysis in MATLAB. I am continously recording the force and position information from a 2 DOF actuator.  Thanks so much!

[trouinky]

Well at >1kHz, you can't use scan mode (real convenient b/c you don't have to build an FPGA VI), so that's off the table.  Decide what your rate will be and we'll figure out how to get the timing right so you get all the data you need...

What's attached is a "simulated" version of your program (the host file saves the data to the default Windows LabVIEW data folder, you can easily change it).  By simulated, I mean your chassis is simulated in the project.  I put a couple other pair of sample programs in there to show you an IRQ method of sending data to the host so you don't lose any data.  The way your program works, the FPGA is running at whatever speed but you only pull a single set of data every time the host loop turns (so you're missing a lot).  This is where the FIFO will be used so you are grabbing chunks of data instead a single set . . .

You'll want to explore how to save the data stream (for instance, after a file gets to a certain size, LabVIEW can start a new file and increment the name . . .).

Play with this and decide on your DAQ rate (should be at least twice as high as the frequency content of what's in your measurement, easy probably to go 4x).  Check some literature on force sensors and what frequency others have grabbed this data.  You might be surprised it's not as high as you might think.

[Moris]

Thanks very much for the files. While loading the project, it could not find this file "niLvFpgaEmulationMode.ctl" but I could run it anyways. Not sure if I am missing anything...

So, if I use Force Sensor 2, where IRQ method is used,  Will I not be losing any data? Or do I still need to use FIFO to avoid losing data?

Thanks,

Moris

[trouinky]

The IRQ method just makes sure that there is a data grab by the FPGA then handoff to the host (whether RT or PC).  It's going to be dictated by the speed of the host, so it's really for slower communication of data between the two, but a reliable "don't miss a single data point" technique.

At rates > 1kHz,  you'll def need FIFO.  This will allow the FPGA to run much faster than the host, sending data to the FIFO memory locations and then the host will, instead of grabbing just a few data points, will grab large chuncks of data to keep up with the speed of the FPGA (DMA is used to carry this out).

So how fast do you need to sample?  If 1kHz is good, you might be able to get away with scan mode, and only use a host program that directly accesses the I/O channels (this is a great, relatively new feature, but limited to about 1 kHz).

[Moris]

Thanks for the clarification.

To save the data, I think 1 KHz is good enough (if not, I shall ask you about FIFO later (-: ). But I want my controller to run at a faster rate (which should be ok because they are independent). 

So, I am safe now with IRQ.

Why did you use loop time? Do I use that information?

-M

Message Edited by Moris on 06-16-2010 02:24 PM

[trouinky]

Those are usually included to report how fast the loop is actually executing.  It's more important on a PC to know this info since the overhead of the OS can affect how strict the loop timing is.  On a RT system, there is no overhead, which is why it can run deterministically, i.e. if you want a loop to run at 10 ms, it will run at exactly 10 ms.  Run the host program and either shake the mouse or move the window around and see how the loop time reported is affected.

Why don't you first try a host program that uses scan mode so you don't have to fret with the FPGA details.  I don't think we can realistically get to 1kHz with scan mode, but you'll learn a few things before heading into FIFO land..

I'm making these fast, so you'll have to add error handling, file save steps, etc.

Realistically you can get 2-5 ms on the RT host and 10-25 on the PC with scan mode.  It's a start, then we'll get fancier.

[Moris]

Thanks for the help.

An error occured while reading the shared variable on the host file. I could run the RT file without any problem. I took a screen shot of the error (please see attached fig.)

I made sure to select the right module (NI9205) which is on the 3rd slot of my cRIO.

-M

[jareds]

Hi Moris,

There are other reasons for that error to occur as well.  You should make sure of a few things:

1) Make sure that you don't have any other FPGA code running on the FPGA.

2) Make that the FPGA bitfile is up to date.

3) Also, if you are using NI-RIO 3.0, you should upgrade to at least NI-RIO 3.0.1.