LAbVIEW FPGA

[ramya850]

I am doing a module in FPGA. The input sampling frequency is 30.72MHZ samples.

Based on that, How should I select the Single-cycle timed loop (SCTL) timer value?

how the output data rate of the module is calculated?

Is it possible to the same SCTL loop time for different input sampling frequencies?

Can anyone explain these in detail?

[Terry_ALE]

It depends on the hardware you are using. 

It will have clocks that you can select to sample in and out approximately. 

Also, your subject is very generic. By giving it a more specific name more people can find it and help you.