Issue with NI-9262 AO Module

[KieranW]

Good day,

I'm having an issue with outputting data on the 9262 module.

To set the scene - I have a memory item that contains fixed point data for a waveform - the fixed point data is of the same type as the expected input of the FPGA I/O node for the 9262 module. The loop on the FPGA main that takes the data from the FIFO and stores it in the memory item is attached called "FPGA Waveform". This saves a new waveform when the waveform settings are updated.

The main FPGA loop is also attached. When an "Alignment" button is pressed, it switches to the alignment state shown and is supposed to loop through the number of samples (the same as are stored in the memory item) and output this data. However, whilst the correct data seems to be flowing to the I/O node - the actual output of the device is 0 throughout.

I've confirmed that the data is not outside the region expected by the AO module (less than 10V amplitude) and the timing is set more than slow enough that update rate should not be an issue. I know that the AO module is outputting correctly as the "standby" state, also attached, has a couple of arbitary values wired to an AO node and I can see these being outputted correctly by the module. I've also tried the examples for the NI-9262 which both operate correctly.

I've tried everything I can think of to make this work - sending it SGL data and letting it coerce, checking there is no error being passed through (there isn't), checking the outputs of the memory item (they are correct) and slowing the rate down as slow as 1 loop/sec but to no avail.

Is there something blindingly obvious I am missing here? Why is the AO module constantly outputting zeros in the alignment case when it is receiving correct data and works otherwise?

Any help would be really appreciated as I'm at my wits end with this.

[LTHC]

Hello Kieran,

If you want to reach 1MHz, the code is a little bit more tricky.

You should start from the reference examples in LabView:

Help\Find Examples... in the search tab look for NI9262.

Mathieu

[KieranW]

HI Mathieu,

I think you might have responded to the wrong thread here. In this case I had an issue with AO nodes not properly generating the signal, nothing time-related.

This was due to having more than one FPGA IO node in the block diagram. Presumably this is to prevent any IO crossover.

As for the 1MHz signal, I am aware that to achieve it you have to use User-Controlled IO Sampling. Implementing this wasn't my issue, my issue was with achieving sufficient synchronisation to other modules.