Is it possible to build a low pass filter on LabVIEW FPGA?

[FrankyD]

I don't know how to implement a FIR filter without floating point facility. Does anybody have a source code or information to implement a low pass filter on FPGA module for 1kHz cutoff frequency?

[Stephan_A]

You might want to check this Tutorial:

Linear Systems in LabVIEW
http://zone.ni.com/devzone/conceptd.nsf/webmain/2F266590B802FEFD8625686500609588?opendocument

Regards

[Christian_L]

I have attached an example of a 15 tap FIR filter running on the FPGA. This is just one type of filter that can be implemented on the FPGA.

For FIR filters the number of taps to be used will determine the design and implementation of the filter in the FPGA VI. The filter coefficients will normally be calculated in the host application and downloaded to the FPGA. In this example the last 15 measurements and the 15 filter coefficients are stored in two rotating arrays in the FPGA VI. The filter calculation itself is a convolution of the two arrays.

To implement a FIR filter with a larger number of taps it may be more efficient to use the user memory on the FPGA to store the coefficients and measurement values. However as the number of taps increase
s the speed of the filter operation will decrease. The 15 tap implementation shown here can execute with the maximum sample rate of the analog input of the 7831R card.

Christian L
NI Consulting Services

[antonio.matar]

Hi Christiian:

I am trying to adapt the filter design that you uploaded, to fit it into the "Frequency Translation Example" for the 5640R Transciever Card.  I intend to filter some frequencies of a signal in real-time.  The output of the filtered signal would be feedbacked in a closed loop to the input through a local FIFO, and also would be transferred to the HOST via a DMA FIFO for observation purposes.

I made the following program (see pic attached) in the FPGA Target, but it seems that the "Rotate 1D array" is not compatible with the "Single Cycle Timed Loop", which I have to use for signal aquisition. (I'm using LabView and FPGA Module version 8.0).  During compilation, the following error appears:

LabVIEW FPGA:  Timing specified in the diagram cannot be met.
Error Code: 61056: Component prim_rotateArray_0076 is not supported in Single-Cycle Timed Loops.

I think I might have to use a "Discrete Delay" (z^-1) to substitute the "Rotate 1D array" component, but I'm not sure about how I must do this.  Could anyone please give me some advice?  Any comments are welcome!

Thank you in advance, sincerely,
Antonio.

[Eli_S]

Antonio.m,

The error you are getting is because the "Rotate 1D array" operation cannot be completed in a single cycle. You may be able to go around this problem by using a regular while loop. (if it doesn't affect the functionality of the rest of the program)