05-07-2018 02:29 PM
Hello,
We are using a cRIO 9066 for real-time control with the main code running on the FPGA and the Real-Time processor being used to handle dataflow between the FPGA and a UI on a networked Host PC. The RT VI calls the FPGA VI through an ‘Open FPGA VI Reference’.
We have been experiencing an intermittent issue where the connection between the RT and the FPGA does not appear to be established. Commands are sent from the UI and processed by the RT using FPGA write nodes, but no effect is seen in the controlled system and no data is sent back by the FPGA either through FPGA read nodes or FIFO reads. We are still able to run the FPGA VI directly under interactive execution, so there does not appear to be anything wrong with the FPGA or code itself.
We have attempted the following in our efforts to address this problem, with no success:
In addition, other projects with the same general structure seem to run fine.
05-08-2018 02:28 AM
05-08-2018 01:13 PM
Hi GerdW,
No errors are present when the FPGA VI is started. The functionality is present while the FPGA VI is run by itself, but there does not appear to be any connection between the FPGA and RT VIs.
05-08-2018 03:16 PM - edited 05-08-2018 03:16 PM
nahawk01,
I believe GerdW refers to checking errors when you open the reference to your FPGA VI in the RT application. I would additionally ask if there are any errors coming out of the read/write nodes in your RT application when the code sends/receives data to/from the FPGA reference.
All the best!
05-08-2018 03:27 PM
How are you starting and controlling your FPGA in your RT application?
How do you know that FPGA is not working?
Are you starting and stopping the FPGA code multiple times during your RT application run?
05-09-2018 10:02 AM
Hi Oscar,
My apologies. I probed the error on the cluster outputting from the FPGA reference on the RT VI and found that it had an error code of 61017. I looked into another forum (https://forums.ni.com/t5/LabVIEW/Error-61017/td-p/2017842) that suggested the use either the bitfile or build specification. When selecting the bitfile, I get a "Block Diagram Error" stating that "Open FPGA VI Reference contains unwired or bad terminal" and does not allow me to run the RT VI. I also tried using the build specification, but that yielded the same result as the first attempt.
05-09-2018 10:05 AM
dkfire,
We are running an RT that calls the FPGA through an open reference. We are connected to a physical system that does not elicit a response when using the RT VI, but does when using the FPGA alone. We are not stopping and starting the FPGA VI while running the RT VI.
05-09-2018 10:38 AM
Hi nahawk,
My apologies. I probed the error on the cluster outputting from the FPGA reference on the RT VI and found that it had an error code of 61017.
This error says: "You need to recompile the FPGA VI!"…
My experience: when running your RT with a startup.rtexe you should set the OpenFPGAReference to point to a bitfile. As long as you are debugging the RT in the LabVIEW IDE you can use the other options of "build setting" or "FPGA VI"…
When selecting the bitfile, I get a "Block Diagram Error" stating that "Open FPGA VI Reference contains unwired or bad terminal" and does not allow me to run the RT VI.
As long as you refuse to attach your VI(s) and the project file we cannot comment a lot on such statements…
05-09-2018 10:41 AM
Hi everyone,
We finally got everything working. This was done by referring to the bitfile instead of the FPGA VI and adding the resource name as an additional input, which solved the broken wire issue. Thank you all for your help!