IP Integration Node Trouble in LabVIEW FPGA

[Akello]

Hello all,

I am having some trouble with the LabVIEW FPGA IP Integration option and was hoping someone could shed some light here.

I am using a simple VHDL code for a one bit, 2-to-1 MUX in order to get acquainted with IP Integration for the LabVIEW FPGA.

In the IP Integration Node Properties pop-up, the syntax check tells me:

ERROR:HDLParsers:813 - "C:/NIFPGA/iptemp/ipin482231194540D2B0CC68A8AF0F43AAED/TwoToOneOneBitMux.vhd" Line 15. Enumerated value U is missing in select.

but I am still able to compile. Once the node is made and wired, I get the solid arrow to run the VI but when I do, I get a Code Generation Errors Pop up that says:

The selected object is only supported inside the single-cycle Timed Loop.

Place a single-cycle Timed Loop around the object.

The selected object in question being my IP Integration Node.

I add a timed loop to the node but although I am able to run the VI, nothing happens; the output does not light up no matter the configuration.

I would say I've tried everything but I can't imagine would the problem could be at this point given that everything compiles and the code is so simple.

I've attached both the VI and the VHDL code. Please let me know if any problems arise as a result of different FPGA boards.

Would really appreciate some help,

Yusif Nurizade

[Akello]

I'm sorry, I don't know why but I cannot add my VHDL code as an attachment, here is the full text:

    library ieee;
    use ieee.std_logic_1164.all;
     
    entity OneBitMUX is
    port(
    first_input:     in std_logic;
    second_input:     in std_logic;
    selector:         in std_logic;
    only_output:     out std_logic
    );
    end OneBitMUX;
     
    architecture main of OneBitMUX is
    begin
    with selector select only_output <= first_input when '0', second_input when '1';
    end main;

[T-REX$ · Accepted solution]

Hey Yusif,

Looks like you are getting into the Single Cycle Timed Loop and never leaving, so the Output indicator never actually gets updated. Try wiring a True constant to the stop condition of the SCTL. Alternatively, you could move all of the controls/indicators inside the SCTL and get rid of the outer while loop. You may run into trouble meeting timing in larger designs without pipeling or optimizing the code if you take that approach however.

[Akello]

TJ, 

Thank you, your suggestion fixed the problem and I get a working VI with both the 1-bit and 2-bit MUXs I created VHDL code for. 

I was hoping you could elaborate on your warning about larger designs. Would this apply to the solution of replacing the while loop with a timed loop or to both of your suggestions. Further, does NI have any literature regarding timing with a IP Node? The white papers I read didn't seem to touch on it. 

Thanks again for your help,

Yusif

[Zach-H]

I believe he was referring to the fact that a single cycle timed loop must be able to execute within one clock cycle. You'll run into timing errors if your IP is not able to execute within that time period, or if any other functions inside of the timed loop were not able to be executed within one clock cycle. 

There is a good explination of the single cycle timed loop here. I think it would be some good background material for you to look through.

[Akello]

Zach,

Much obliged, I will take a look at the link you provided.

Thanks again for the help,

Yusif Nurizade