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I/O access? can you access the hardware design, such as the pins of the FlexRIO

Can I/O pins of the FlexRIO be accessed by code running in a user created CLIP and/or IP Integration node?

 


Certified LabVIEW Architect, Certified Professional Instructor
ALE Consultants

Introduction to LabVIEW FPGA for RF, Radar, and Electronic Warfare Applications
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Hi Terry,

 

I think this depends on what you mean by "accessed." Just to clarify, when you refer to I/O pins you are talking about the physical I/O nodes, as are typically defined by FAM CLIP? Or some other FPGA IO concept (it kinda gets thrown around a lot). The other followup is do you want your user defined CLIP to exist alongside with default FAM CLIP? You could make your own socketed CLIP that replaces the default FAM CLIP that directly interfaces with the I/O and passes all that back to LabVIEW FPGA. However, if you want to keep the existing CLIP alongside your user defined CLIP, then the IO data would have to pass through LabVIEW FPGA and then get fed to your user defined CLIP.

 

IP Integration nodes very specifically cannot directly access FPGA IO. You can still pass the data from IO through LabVIEW FPGA and then into the IP Integration node, though.

 

Just in case you hadn't seen it, here's a useful document on CLIP integration: https://knowledge.ni.com/KnowledgeArticleDetails?id=kA03q000000x0jiCAA&l=en-US.

 

Regards,

 

Cason

NI Applications Engr.

Cassandra Longley
Senior Technical Support Engineer - FlexRIO, High Speed Serial and VRTS
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