LabVIEW

cancel
Showing results for 
Search instead for 
Did you mean: 

How to use CIE and FPGA target on the same cRIO chassis?

Solved!
Go to solution

I've got a cRIO system consisting of a 9074 master chassis with several I/O modules and an EtherCAT slave 9144 unit.

 

I want to run a CIE (see: http://zone.ni.com/devzone/cda/epd/p/id/5333) on the master chassis, this uses the scan engine. At the same time I need to do some very time-critical measurements so I want to use the board in Hybrid mode, utilizing the scan engine and FPGA at the same time (as described here: http://digital.ni.com/public.nsf/allkb/0DB7FEF37C26AF85862575C400531690.

 

But as soon as I add the FPGA target to either one of the chassis, the CIE functionality on that chassis ceases to function. After some digging I've found that the CIE can no longer initialise the modules belonging to the chassis that has the FPGA target on it. Error in the CIE Init method is: 65700 (undifined). This occurs when trying to use "To more specific class" on modules that are configured with an FPGA target on it.

 

Does someone know what exactly causes this problem and maybe supply a solution/workaround?

 

Great thanks in advance.

0 Kudos
Message 1 of 7
(3,852 Views)

Hi all,

 

I'm having an almost identical situation. I need to run my chasis in hybrid mode in order to use an RS-232 module that requires FPGA code. Like Wyth, I found the problem to occur when using the To More Specific Class function, throwing error 65700. The reference library description specifically says that the CIE supports using FPGA VIs, but this is obviously not the case. Any lead at all would be very helpful here as I've tried everything I can think of.

 

Thanks

0 Kudos
Message 2 of 7
(3,810 Views)
Solution
Accepted by topic author Wyth

Hybrid mode requires that you have a compiled bitfile running on the FPGA to be able to read Scan Interface IO Variables.  Moving the module from the FPGA target to the RT target will enable the Scan Interface for that module, but the chassis will still be in LabVIEW FPGA Interface mode.

 

18491iACA42C3006BA1008

 

To get just scan mode access for the chassis, right-click the chassis in the project and choose Properties.  Then, change the Programming Mode to Scan Interface.  If you still want to use FPGA programming and the Scan Interface together (hybrid mode), you will need to compile a bitfile (empty if you don't want any programming on the FPGA yet or containing your FPGA code).  By compiling, the scan mode module support for the modules under your RT chassis will be compiled into your custom bitfile.  Then, on your RT VI, you will need to use Open FPGA VI Reference to your newly compiled VI.  Once this VI is deployed and running, you will get data from your the CIE.

 

For more information, see this KnowledgeBase article as well as the CompactRIO Scan Interface Reference and Procedures.

Donovan
Message 3 of 7
(3,804 Views)

That fixed it! Thanks so much.

0 Kudos
Message 4 of 7
(3,794 Views)

Ah yep, it wast the empty bitfile. Thanks for the reply.

0 Kudos
Message 5 of 7
(3,784 Views)

I have a very similar problem. I have been battling this issue for two days now. I'm using the CIE as part of the Machine Control Reference Architecture (MCRA), and cannot get the FPGA to play nice with the cRIO Scan Interface. If I set the Chassis Programming Mode property to Scan Interface, CIE works perfectly. Then I switch it to FPGA and run my FPGA code and it does not work. I get error 65704 (To More Specific Class in CIE Init.vi). I've tried the FPGA VI alone and it works fine.

 

I've tried compiling the FPGA with the programming mode set to both Scan Interface and FPGA. I've tried placing the Open FPGA block before and after the CIE Init block. I've tried Deploying about 100 different ways. Nothing has worked. Is there something I am missing??

 

Thanks in advance,

Richard

 

 

_______________________________________________________________
"Computers are useless. They can only give you answers." - Pablo Picasso
0 Kudos
Message 6 of 7
(3,547 Views)

Update:

 

I recompiled after changing the Programming Mode to FPGA (even though LabVIEW said the bitfile had not changed) and now I get error 65702 (To More Specific Class in CIE Init.vi). In addition, as soon as I close the FPGA reference, I lose my network connection to the cRIO system. I put in a delay just to be sure, and indeed the connection is lost right after (plus a few seconds for a timeout) I close the FPGA ref. What is going on?!

 

Again, the CIE code works fine when I use Scan Interface mode and no FPGA code. The FPGA code works fine when I do not use CIE and run in FPGA mode. When I change to FPGA mode and run both the CIE and the FPGA code, the whole thing barfs.

_______________________________________________________________
"Computers are useless. They can only give you answers." - Pablo Picasso
0 Kudos
Message 7 of 7
(3,541 Views)