Hi!
I am using two FPGA 7962R (flexrio) with each 6581 terminal board in PXIe-1082 chassis. My problem is how to synchronize two 7962R digital output with PXIe-1082 chassis backplane signal Dstar* or Clk10 or DAQ signal.
Actually I tried the synchronization with one DAQ counter clock (confering 'Gen Dig Pulse Train-Finite_NI. vi') , and get the signal PXI-Trig0 by source terminal and target terminal connection, but that one does not work properly. Especially, one trigger signal in HOST to set the starting point of each FPGA (7962R), make error by depending on the trigger signal value(Hz value and Timed loop clock in FPGA vi). It was very tricky and not reliable. (I am attaching figure files as explaining the situation)
My aim is simply to use two FPGA 7962R Digital output as one FPGA, for controling X-axis, Y-axis with each FPGA, while able to change each FPGA (X-axis, Y axis) digital output value. Because the synchronization is not correct, X,Y axis control with Two FPGA currently is out of target if I use simply while-loop design in HOST and timed-loop design in FPGA vi. What is correct design to synchronize the two FPGA 7962R without using PFI line, only with PXIe-1082 chassis backplane signal and able to change the digital output value? Please let me know any idea for HOST vi, FPGA vi programming.
Many Thanks
