How to simulate external hardware in LabView FPGA ?

[Blup1980]

Hello,

I have a NI 7952R connected to a 6583 IO module.

This IO module is connected to a digital sensor that continuously sends patterned data.

I am developping the code for the FPGA and I would like to know how to perform a cycle accurate simulation of the whole system.

There is an example for a cycle accurate simulation of the labView -> FPGA interface, but it doesn't include the behavior of an external hardware connected to the FPGA IO module.

Now I have a VHDL simulation model (not synthetisable) that describes my sensor. How to include that into the iSim cycle accurate simulation?

Do I have to alter the 6583 IO module CLIP files by including my sensor description into it?

[Topper_Harley]

Hi,

please have a look at these documents:

Cycle-Accurate Simulation in LabVIEW FPGA

http://www.ni.com/white-paper/12917/en/

Cycle Accurate Simulation of LabVIEW FPGA Designs Using ModelSim

https://decibel.ni.com/content/docs/DOC-12005

Cycle-Accurate Simulation with Xilinx ISim

http://www.ni.com/white-paper/12942/en

[Blup1980]

Thanks.

But all theses documents describe how to simulate the FPGA with the stimulus applied to the front pannel of the FPGA vi.

What I would like to achieve is the simulation of the FPGA with the stimulus applied to physical pins of the FPGA, or more specifically, to an I/O module attached to it.

This doesn't seem to be explained in any examples from NI.

I should be possible because it is written here:

http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgaconcepts/fpga_sim_vhdl_framework/

" (Optional) I/O Stimulus/Response—This part of the model contains code that you add to simulate FPGA target I/O. "

But it's not described how or where to do it.

[Topper_Harley]

I am sorry but I do not see where it says that you can use real FPGA I/O with your simulation.

Please read carefully: "(Optional) I/O Stimulus/Response—This part of the model contains code that you add to simulate FPGA target I/O. "

My interpretation of this sentence is that you can you can use calculated/recorded signals to simulate your FPGA I/O. This may be the reason why you found no documentation or examples how to do it.

[Blup1980]

> My interpretation of this sentence is that you can you can use calculated/recorded signals to simulate your FPGA I/O.

Yes this is exactly what I want to do. I don't want to connect the real hardare to my FPGA system without proper testing of the FPGA code in simulation first.

But 90% of what my code is doing is timing generation for the external sensor, and data decoding of the external sensor. Thus non "cycle accurate simulation" is useless here. And independant simulation is useless too, without stimulus from the sensor, the FPGA does almost nothing.

I have a set of VHDL files that describes the behavior of my external sensor and I would like to use it to stimulate my design in simulation.

What I want to do seems to be what they call  "I/O Stimulus/Response". Whithin the text is seems to be in the same context.

My only issue is that I don't see where to include my sensor VHDL code into the test bench that LabView generated for the use of iSim.

[Topper_Harley]

Thank you for your answer, I think now we have a common understanding of your intent.

Your I/O simulation model is integrated via a clip or ip integration node:

"In addition to VHDL code for the FPGA VI, you must provide simulation models for any IP you include through the CLIP and IP Integration Nodes. You specify the models for CLIP simulation and the IP Integration Node simulation through their configuration wizards."

Taken from:

Introduction to Cycle-Accurate Simulation

http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgaconcepts/fpga_simulation_intro/