How to run multiple VI or bitfile on cRIO FPGA

[pbpatel]

HI

 I have on host vi which has two subvi one containing control logic (test.vi) and other vi for I/O debugging(debug.vi) .If I make two different FPGA VIs named as  testfpga.vi and debugfpga.vi. If test.vi is running on host pc i want to load testfpga.vi and when debug.vi is running then debugfpga.vi Is it possible?

[10Degree]

pbpatel,

You can use the "Open FPGA VI Reference.vi" to dynamicly load bitfiles in your FPGA target at runtime.  Use the "Close FPGA VI Reference.vi" if you want to open a different reference (ie, switch between your testfpga.vi and debugfpga.vi).

-cb

[pbpatel]

Thanking you for your reply,

But how can I download multiple bitfiles in cRIO FPGA. I mean "Open FPGA VI Reference.vi" will load bitfile from Host computer to cRIO or it will be on cRIO memory. If it is in cRIO memory then where can i put this bitfiles in cRIO.

[DarkLordOfG]

Did you ever figure this out?  We have a similar need.  We want to dynamically load the bitfile at runtime from the RT not a host.

[crossrulz]

Just put the bitfiles somewhere on your cRIO that you can easily get to and then dynamically choose which bit file to load.

[Jacobson-ni]

The function crossrulz is talking about is the Open Dynamic Bitfile Reference

http://zone.ni.com/reference/en-XX/help/371599L-01/lvfpgahost/open_dyn_bitfile_reference/

Because I haven't seen anyone talking about this, I want to mention that you cannot have two bitfiles running on the FPGA at the same time. You can switch between bitfiles at run time but it will take a few seconds before you can actually communicate to the FPGA. If you are going to do this, make sure you are switching bitfiles during the system's downtime or between tests and not when you have to be actively controlling outputs.