How to generate a programmable CLK up to 32MHz with an FPGA card like PXI-7831R?

[Peterpaul]

Hello,

i need to generate a programmable Clock on the FPGA card, which can be used for up to 32MHz.

I already used single-cycled-timed loops with which iam able to generate faster clocks but they are not programmable since one Channel is only allowed to be connected to one time domain at a time.

At the moment the fastest i get is a 15MHz clock with a normal while loop, which has a timer inside to delay it for slower CLK frequencies. The timer can be disabled by a case structruce, since even if the delay is 0 ticks, the fastest CLK speed is 10 MHz.

This only works with an derived CLK of 120MHz which is the maximum iam able to achieve on my system.

In all cases i use a single inverter inside the loops which keeps on inverting its own signal.

(Labview 8.2, PXI system)

Iam open to any ideas since i have run out of them.

[Christian_L]

What resolution do you need on the clock rate that you want to generate? The example below is a single cycle timed loop set to run at 100 MHz and can generate any clock rate with a resolution of 10 ns. The fastest clock that can be generated is 2 cycles of the SCTL (50 MHz). From there you can generate a clock at 3 cycles, 4 cycles, etc.

Message Edited by Christian L on 06-27-2007 02:51 PM

[Peterpaul]

Thanks for your idea, it works but iam facing some other problems now.

Basically i need frequencies in the form of 32MHz,16MHz,8MHz..........

I got this frequencies with your program idea by setting the clock to 64MHz. The problem is now, i was using an occurence inside the clock function to be able to synchronise other parts of my program with the clock. By using the 64MHz Clock domain iam not able to use the occurence anywhere else in the program anymore since i cant use 64MHz as a toplevel Clock on my device (only 40,80,120 MHz top level clocks allowed).

So now i need an advise on how to synchronise other parts of the program (which do not fit into single cycle loops) with the clock.

Thanks in advance

Max W