How to determine FPGA program run speed?

[Eternal_Newbie]

Hi,

I have been tinkering with LabView FPGA for a while now and I can't seem to find out a good way to determine the speed my FPGA is running at. I am currently using a NI cRIO-9073 that is rated at 40MHz. I know anything I put inside a timed loop will be ran in one tick, but LabView refuses to do any inputs and outputs unless it is in a regular while loop. I tried putting in time counters to give a sense of how fast the FPGA program is running at, but that requires extra resources on the FPGA, compile time, and doesn't seem too reliable. The reliability part is probably due to whatever starting state the FPGA program starts up in reference to the inputs I am providing. I have 3 inputs so I could have just simulate the input and do a simulated timing all on software, but that would defeat the purpose of getting a real operating speed and this method won't work for lots of inputs due to geometric increase in input state combinations.

Does anyone know how I can find out how fast a program running on a FPGA really runs at?

Thanks in advance.

[MarcoMauri]

---

@Eternal_Newbie wrote:

LabView refuses to do any inputs and outputs unless it is in a regular while loop.

---

Hi!

In a Single Cycle Timed Loop you can set a Digital Output.

So for instance you can switch an output state and check it using an oscilloscope (check the maximum refresh rate of the DO and in case 'downconvert' the frequency of the loop, i.e. change the state of the DO every 100, 1000, ... ticks).

[Eternal_Newbie]

MacroMauri, your method is definitely better than doing it in simulation. It's good to know digital output can operate inside a single cycle timed loop. Lucky that I do have a digital input/output module 🙂

I tested my current FPGA by increasing input signal frequencies. The results are still good at 500kHz with digital inputs and 25kHz with analog inputs. For my current need of ~1kHz it is definitely enough. Next time or if I get the chance, I will definitely try it out and see how it goes.

For future cases when all ports are used or no digital ports, I wonder if there is another method to find the operating speed. (I guess one can use the FPGA LED as the digital port, but...)

[dkfire]

As you have not posted any code or specified that your input and output are that you are trying to put in a SCTL.

One limitation is that analog input and output takes more than one tick ( I think it is 37 for output and 170 for input )

You can always get the number of ticks that a while takes by a little debug with the Tick Count vi.

[Christian Mergl]

Hi,

First of all, I disagree with the method MarcoMauri suggested. He is right that a DIO Node can be placed within a SCTL since it only takes one Tick for its execution. But in the background there is a Synchronization-Register used for this capability, since the fastest C-Series module "just" reaches something about 18MHz (55ns) update rate.

Regarding the timing of an SCTL. If configured for the 40MHz Base Clock it will run with 40MHz and a jitter of something about 250ps, and this is reliable since we are talking about an FPGA and not an processor running an OS.

I agree with dkfire that an typical AI takes about 170 Ticks (module specific) and a typical AO takes about 37 Ticks (also module specific). This is one reason why you cannot place it into a SCTL.

On the other Hand I am not sure if I understood the main question

If you simply need to get the actual loop rate make a benchmarking using the Tick-Count. This does not influence the timing of your other code since it will be implemented truly parallel.

Hope this helps,

Christian

[Eternal_Newbie]

I have made a bunch of revisions since then and I don't really remember which is the one has the tick counter if I haven't accidentally saved over it with my later revisions 😛

In any case, here is the overview for those who wanted to know more about the program.

I have 3 while loops running in parallel (A, B and C). Loop A samples my 3 analog inputs continuously and transfers the input values to Loop B. The 3 input signals are of different frequencies so my Loop B is actually placed inside a flat sequence with some waiting logic to guarantee the main logic starts at the same input state. On every cycle of Loop B, an updated result will be send to Loop C for output. All data transfers between loops are through local variables.

For the version I tested the tick counter in, I only have the 3 parallel loops (A, B, and C) and no flat sequence (yes, the result will be all over the place since the program will be confused without a fixed starting state reference). The tick counter was placed inside Loop B with an indicator showing the maximum difference in tick count between each cycle. However, the value changes each time I reboot the FPGA so the tick counter method is not reliable. At least not the way I am doing it. My thoughts on the unreliable tick count is probably caused by the state of the inputs when the FPGA is rebooted.

P.S. I used the SCTL in my main logic since I didn't know digital outputs can be in a timed loop and I think I also linked the result to a FPGA to Host variable for debugging.

[Eternal_Newbie]

Hi Christian,

I am not sure what you mean by benchmarking with a Tick-Count. I have tried putting the tick counter in its own parallel while loop, but tick counters roll over its last value for the next loop cycle. I ended up getting multi cycle time with possible overflow. I haven't explored any of the overflow things so I am clueless on that front. On the other hand, setting all the loops to single cycle run will give me a time for that particular run, but there will be logic in the main program that might be skipped due to whatever input the single sampling returns. (e.g. all 3 inputs high would use 10 logic gates in main program vs all 3 inputs low would use 20 logic gates)

I think you do understand my main question based on your response 😜

How to find out what speed or frequency a FPGA program runs at after it is compiled and loaded onto a FPGA. Of course the worst case speed 😉

Thank you for all the suggestions and comments you guys have given. As I said before, right now this isn't a show stopping issue for me at the moment, but I just think it will be useful to know. I'll post more when I find out something new.

[MarcoMauri]

---

@Christian_M wrote:

Hi,

First of all, I disagree with the method MarcoMauri suggested. He is right that a DIO Node can be placed within a SCTL since it only takes one Tick for its execution. But in the background there is a Synchronization-Register used for this capability, since the fastest C-Series module "just" reaches something about 18MHz (55ns) update rate.

---

Exactly. That's why I suggested to downconvert the frequency, meaning you can update the digital output every, let's say, 10 ticks...

The reason for this benchmark is not to 'measure' FPGA clock frequency, but to see, using a scope, what a FPGA can really do.

[Christian Mergl]

@ MarcoMauri: Just wanted to point that out for other users since they might not be familiar with the IO Timings

@ Eternal_Newbie: I get more confused with every new post from you what exectly does not work. Maybe you could post your code and describe what loop or timing you want to benchmark?

Christian