How CompactRIO DMA host to target works?

[Psy4trip]

I try to transfert 2Mbits Image between 2 compactRIO (cRIO-9012). So, firstable, I load data from binary file to RT FIFO (512x256x16bits) in low critical loop (100ms). Next, I send data to FPGA with FIFO DMA (Host to Target, 2047 elements) in high critical loop (5ms). FPGA wait signal request from the other compactRIO to send data on high-speed synchronised communication line (2MBits/sec). The other FPGA read data and send directly in FIFO DMA (Target to Host, 2047 elements). The receiver transfert data in RT FIFO (1024x128x16bits) in high critical loop (10ms) and they send to Host Computer on Network Shared Variable (131072x16bits) in low critical loop.

So, my problem is multiple:

I don't really understand how work DMA Host to target because when the FPGA wait request signal, I wrote first data (nx512, n>2...30) in RT, I verify the "Empty Elements Remaining" but only one frame of 512 value seem wrotten on FIFO. So, if you are an explanation

On the receiver CompactRIO, I wait to have 1024 Value in DMA to transfert data in RT FIFO, but sometimes, I have some more value in "Elements Remaining".

The last problem is on Network Shared Variable. The fisrt occurence is always empty and there is a shift on variable...

In conclusion, and with all this problem, I arrive sometimes to receive correct image. But it isn't really stable and after that data are shift, I must restart all devices. I ever try with classical FPGA termial and internal FPGA FIFO but it doesn't work. So I will try to monitoring the sending data number with RT High critical loop, but i think is to heavy process and it doesn't usefull. Last details is that my RT vi isn't standalone for the moment, but i would like to see a well and stable processing before a standalone deployement.

So, about the FIFO DMA host to target, I dont understand why they aren't an example or a tutorial or anything in "Developer Zone".

Thank for you answers

Later,

Psy4Trip

[ElRambo]

Hi Psy4trip,

DMA FIFOs transfer data from the FPGA directly to memory on the CompactRIO RT controller. DMA FIFOs can stream large amount of data to and from the host VI. This allows the FPGA to use the host RAM as if it were its own. This offers significant performance advantages over using multiple loops, a local FIFO, and reading indicator to transfer data from the FPGA to the host.

With DMA FIFOs the host computer processor can perform calculations while the FPGA target transfers data to the host computer memory. FPGA targets that support DMA FIFOs have direct access to write memory on the host computer withou involving the host computer processor. Without DMA FIFOs, you can transfer data only through the host computer processor. LabVIEW performs DMA transfers through bus mastering. FPGA targets that support DMA FIFOs can master the PCI bus. The FPGA target controls the PCI bus and accesses memory directly without needing to access the host processor.

A DMA FIFO consists of two parts : an FPGA part and a host computer part. The FPGA part of the DMA FIFO is stored in memory on the FPGA. The FPGA VI wrotes the FIFO one element at a time with the FIFO Write function or reads the FIFO one element at a time with the FIFO Read function. The host computer part of the DMA FIFO is stored in memory on the host computer. LabVIEW uses a DMA Engine to connect the two parts. The DMA Engine includes driver software and hardware logic. When the DMA Engine runs, it transfers data between the two parts of the FIFO automatically so they act as one FIFO array. The host VI reads from or writes to the FIFO one or more elements at a time with the Invoke Method function.

Regards,