High throughput CORDIC speed (FPGA)

[Intaris]

I'm currently refactoring some code and am looking into increasing the execution speed of a modulator to be able to multiplex more units without having to neccessarily utilise more resources ont he FPGA chip.

I have found that pipelining the High Throughput multiply helps achieve higher clock rates (I'm currently at 120MHz) but when trying to get to 160MHz, the CORDIC algorithm becomes the bottleneck and starts throwing timing errors.

I'm thinking maybe that the multiplication which is performed by the CORDIC for automatic Gain Compensation is NOT pipelined and is leading to my problem?  I've removed this option from the CORDIC node and am now doing the multiplication myself after the function which I can then pipeline.

What kinds of speeds should be achievable with the High throughput CORDIC nodes?

On a similar note, are there any more concrete informations on the achievable clock rates when pipelining the high throughput nodes (CORDIC, Multiply etc.).  I found one document on the web which noted that up to 7 pipelining stages can be required for maximum multiplication throughput with the DSP48.  Any hints on where to find more such documentation?

I'm using a PXIe-7965R with LV 2012 SP1.

Shane.

[Intaris]

Is the implementation for Virtex 5 Targets the DS249 LogiCORE IP CORDIC V4.0?

If so, then THIS document contains very detailed information about the algorithm.

Shane.

[Intaris]

I have it up to 315 MHz, if I can get 320 I'll be more than happy.  326 is the max clock on my device anyway.....

Although we'll be using the code at a slower rate, the steps required to get to that rate are very interesting.....

[Intaris]

Yaay, 322MHz compiled.

Cool.

Shane