GPS PPS counter independent from FPGA 40MHz Onboard clock

[JCC_(SK)]

Could you give me some advice or point me in right direction?

I need accurate time/tick counter synchronized by GPS PPS synchronization signal.

I have got S.E.A. GPS cRIO Module which generate PPS signal to FPGA backplane. PPS signal rising edge precisely indicate the start of second.

When I measure number of ticks from 40MHz FPGA Onboard clock during one (PPS) second then number of ticks is not 40,000,000 ticks but something like 39,999,800 ticks.

I want measure accurately time between rising/falling edges of Digital signals. Because 40MHz FPGA onboard clock are drifting I can not use it.

How could I implement my own ticks counter witch will be tided with GPS PPS signal?

I don't expect that I could tune 40MHz FPGA on board oscillator.

Should I create my own counter which will increase counter by value 1.000,005 (40,000,000/39,999,800) every tick and this counter will run in Timed Loop (time base 40MHz FPGA onboard clock). Increment value (1.000...) will be updated every second depend on PPS vs FPGA clock drifting.

My configuration: cRIO-9025, cRIO-9116, S.E.A. GPS+ cRIO module, high speed DIs NI 9402, RT/FPGA LabVIEW 2011

Looking forward to hearing form you.
 Peter

[Daniel_Thomas_NIUK]

Hi Peter,

The specified Accuracy of the cRIO-9116 clock is ±100 ppm (max). This would result in an acceptable variance of 4kHz. You are seeing a variance of 200Hz which fits with the expected specification of the cRIO-9116.

As you expected there is not on option to tune the 40MHz FPGA on board oscillator

Your suggested solution does certainly sound plausible, have you begun to implement this yet?

Kind regards,

[JCC_(SK)]

Hi Daniel

Thank you for your reply.
I didn't begin to implement my solution yet. But I will have to start and soon 😞

I wanted to know if there are another kind of solution which I could use.

I didn't find any articles about LabVIEW FPGA and PPS synchronization and time/ticks measurement.

Have you or somebody else, same good advices? 🙂

 Peter

[JCC_(SK) · Accepted solution]

Hi all

this could help you.

FPGA Timekeeper

• http://digital.ni.com/public.nsf/allkb/EFDC35727D4F2CC086257A0700693003
• https://decibel.ni.com/content/projects/ni-timesync-fpga-timekeeper

(I don't understand how this could be published on 23/05/2012)