Frequency scaling down of the signal

[GerdW]

Hi Navin,

where did you set those "3MHz clocks"? They are not visible in your images…

(Unfortunately I cannot examine your code in all details because of some missing hardware support.)

[Navin4561]

Hi GerdW,

i have set the clock1 frequency in FPGA base clock properties window and here i am attaching image for your reference. please check it.

[GerdW]

Hi Navin,

as I don't have experience (and hardware drivers) for this special kind of hardware I'm out of suggestions!

With a cRIO FPGA I would create a derived clock from base clock - or use a simple Wait function inside a plain WHILE loop…

[Navin4561]

Hi Gerdw,

i have generated the derived clock with 3MHZ for FPGA, signal frequency is 320KHz, output frequency  is ok now but output signal on the CRO seems like stepped sine signal..

i keep increasing the #samples also still it couldn't be solved

how to smoothen the signal can anyone please suggest me

regards

navin

[GerdW]

Hi Navin,

do you mind to provide the current state of the project?

Can you attach some images of the waveforms you are worried about?

[Navin4561]

Hi GerdW,

i am updating the state of the project here

Now my timed loop is running at frequency is 3MHz SCTL, signal frequency is 320KHz @fs =3MHz

now i am getting output frequency almost equal to input signal frequency, but wave form is not a smooth sine wave, itseems like stepped sine signal. 

Here i am attaching the project file and images of the signal on CRO..

please have a look at it and help me out

[GerdW]

Hi Navin,

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@Navin4561 wrote:

signal frequency is 320KHz @fs =3MHz

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At fs=3MHz and sine frequency of 320kHz you get just 9 samples per period: I would expect nothing else than a "stepped" output signal…

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@Navin4561 wrote:

wave form is not a smooth sine wave, itseems like stepped sine signal.

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I don't know where you see something like a "stepped sine wave". All I see is a ramp (aka sawtooth) signal with just 3 or 4 samples per ramp…