FlexRIO DRAM problem in Labview FPGA 2010

[irad]

Hello,

I am just switching from Labview FPGA 2009 to Labview FPGA 2010 and I am having compilation problems with very simple projects that shouldn't fail to compile.

I am using a FlexRIO 7965R board as a target. Initially, I just wanted to recompile a project that was working fine under Labview FPGA 2009. When it failed, I drastically

simplified it to isolate the source of error. I ended up with what is attached. In this very simple VI I just write some values into DRAM banks in one timed loop, read them out in another and send them through a Target to Host DMA FIFO. Both loops are quite slow running at only 40 MHz. Previously, I was able to compile VIs with DRAM clip nodes in timed loops running at 100 MHz without any problems.

The compilation fails with this summary:

"Compilation failed due to resource overmapping"

although it should fit easily.

The error is definitely related to DRAM. This s what Xilinx log says:

"ERROR:Place:543 - This design does not fit into the number of slices available in this device due to the complexity of

   the design and/or constraints.

   Unplaced instances by type:

     IDELAYCTRL    21 (48.8)  "

Then it lists these instances (about 20):

   0. IDELAYCTRL Puma20DramMainx/GenBank0or1Mig.u_ddr2_idelay_ctrl/u_idelayctrl_MapLib_replicate0

   1. IDELAYCTRL Puma20DramMainx/GenBank0or1Mig.u_ddr2_idelay_ctrl/u_idelayctrl_MapLib_replicate1

   2. IDELAYCTRL Puma20DramMainx/GenBank0or1Mig.u_ddr2_idelay_ctrl/u_idelayctrl_MapLib_replicate2

  .........

Both DRAM banks are configured with the clip node for 128-bit FIFO version v1.1.0. I also tried using the legacy version v1.0.0 but it didn't make any difference.

It looks like I have some configuration problems I can't identify or there is something wrong with the DRAM clip node in Labview FPGA 2010.

Any ideas on what could be happening here? Any help would be much appreciated.

Regards,

Ivan

[BrowningG]

Hello Ivan,

It looks like in your project you are using both the NI 5761 adapter module and DRAM.  We have seen a few cases where certain combinations of DRAM, adapter modules, and FlexRIO FPGA targets in LabVIEW FPGA 2010 have caused some resource overmapping errors of the IODelayCtrl components used in the adapter module and DRAM CLIPs. Due to a bug, certain constraints inside of the CLIP cores are misinterpreted by the ISE compiler causing this overmap error when you switch to LabVIEW FPGA 2010. 

This was reported to R&D (# 258076) for further investigation and to create a long term fix.  In the meantime, for this specific issue please use the following knowledgebase article to apply a patch to your FlexRIO fixed logic files.  This patch updates some of the constraints used by the DRAM to ensure that the Xilinx compiler can properly interpret them. There are more details on your issue in the knowledgebase as well. 

Knowledgebase 5E4FNCDP: Error, “Compilation Failed Due to Resource Overmapping,” When Using NI FlexR...

If you do run into any other issues regarding IODelayCtrl components, feel free to reply to this forum topic to let me know about them.

[irad]

Thank you Browning. This is exactly the problem I had. I installed the patch and compiled a couple of projects and it looks like the problem went away.

Regards,

Ivan