Feedback Node Delay Issue in LabVIEW FPGA on PXIe-7972R — Real-Time Filter Implementation

[Arash.g]

Hi all,

I’m a research student at UNSW working on a quantum optics project involving real-time phase estimation and lock, using the NI PXIe-7972R FPGA and LabVIEW FPGA.

I’ve built several digital filters from scratch in LabVIEW FPGA for this, including a first-order static state-space filter, a second-order static filter, and a second-order adaptive notch filter.

In all cases, I’ve noticed that my feedback nodes only work as expected if I set their delay to a value higher than 1 (e.g., 10 or more clock cycles). If I use the default delay of 1, the filter output ends up identical to the input, there’s no real filtering happening. When I increase the delay, the filters start working, but I’m not sure why this is the case.

Does this mean that my while loop (or filter logic) is taking more than one clock cycle to compute, and so increasing the feedback node delay just “gives it more time”? Is this a sign that I should be using pipelining (which I haven’t implemented yet)? What’s the best practice for filter implementation and timing on the 7972R FPGA to avoid this issue? Any other issues I should be aware of when implementing real-time feedback/filters on this platform?

I’ll be moving my MATLAB simulation to LabVIEW soon and want to make sure I understand these timing and pipelining issues before going further.

Thanks in advance for any help or advice!

Best regards,
Arash Ganjei

 

 

[GerdW]

Hi Arash,

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@Arash.g wrote:

In all cases, I’ve noticed that my feedback nodes only work as expected if I set their delay to a value higher than 1 (e.g., 10 or more clock cycles). If I use the default delay of 1, the filter output ends up identical to the input, there’s no real filtering happening. When I increase the delay, the filters start working, but I’m not sure why this is the case.

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In the upper image you wired the "Enable" terminal of the feedback nodes: as long as it is FALSE the feedback node will NOT take the value of the current iteration. It will only take values for TRUE, so only at the 400th iteration…

In the 2nd image you use a plain feedback node - you could use a simple shift register instead.

Where did you configure any nodes for "delays larger than 1"?

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@Arash.g wrote:

I set their delay to a value higher than 1 (e.g., 10 or more clock cycles). 

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• Those nodes don't need "clock cycles", they are counted in iterations.
• The loop around defines the timing! As you use plain while loop they will run as fast as possible, using the timing function inside the loop. To define timing more strictly you should use the SCTL (SingeCycleTimedLoop) instead!

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@Arash.g wrote:

Does this mean that my while loop (or filter logic) is taking more than one clock cycle to compute, and so increasing the feedback node delay just “gives it more time”?

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Your while loops will definitely take more than one clock cycle to execute - because they are plain while loops!

Each "stage" will take one clock cycle, so the 2nd loop will take 3 cycles (multiply, add, multiply) plus the overhead of the loop itself…

There is a help on FPGA programming with LabVIEW and you should read it!