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FPGA timing far from promises

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My application focus on measuring time between digital TTL events. The hardware used consist on cRIO9068 and high speed 9402 module.  Since the hardware channel can run up to 16MHz and FPGA single loop can achieve 80MHz clock, I aspected to have for this application an accuracy around 5 ticks (1 ticks = 12.5ns = 1/80MHz, 5 ticks =62.5ns =1/16MHz).

Well i can test the application feeding squares to 9402 via a function generator (high quality one). While the accuracy on time regarding only rise  (or only  falling) TTL  events is quite good (10 ticks at 1kHz ) once i use to deal with both rise and fall events the accuracy became around 60 ticks.

Who is guilty here ?

However from what i see the paper specifications for these hardaware are not meet

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Message 1 of 9
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Hi Rozzilla,

 

Who is guilty here ?

Well, most times the problem exists between keyboard and chair 😄 (PEBKAC)

 

Do you mind to show your VI (and full FPGA project)?

Without any more information from your side we cannot help you with your problem…

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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Message 2 of 9
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most time maybe not this since it so simple to manage, i cannot share the code since this is not arduino forum (even ....)

 

 

 

 

Untitled.jpg

 

 

 

 

 

 

 

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Message 3 of 9
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Hi rozzilla,

 

when you cannot share the code we cannot help with suggestions!

(What help do you expect for your code problems when you don't show the code?)

 

We even cannot see basic things like how you configured the TWL…

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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Message 4 of 9
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TWL ??

putting in strange words doesnt help.. im not a beginner.

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Message 5 of 9
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Solution
Accepted by topic author rozzilla

@rozzilla wrote:

TWL ??


I think GerdW meant "Timed While Loop" although I haven't seen that abbreviation before (and I've been using LabVIEW FPGA for a long time).

 

We really do need to see your code, as well as the project file to see how you configured your top-level clock and any derived clocks, in order to provide any assistance.

 

I would discourage you from using comparison functions (such as greater than/less than) for comparing booleans. Use standard boolean logic (AND, OR, etc) instead.

Message 6 of 9
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maybe i wasnt too detailed but offcourse the code is compiled (correctly) with a single cycle timed loop with a derived (x2) clock of 80Mhz. I tried all the code possibilities regarding rise and fall reckon with no better luck

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Message 7 of 9
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You marked the thread as solved - did you solve the problem, or did you mark it solved by accident?

 

If you have not in fact solved the problem, unfortunately there's nothing more we can do to debug the problem without more information about both your code and your goal. All programmers, no matter how good they are, make mistakes occasionally, so we cannot trust that your code is correct based only on your statement that it is. If it turns out that you are correct that it's the hardware at fault, unlikely as that may be, we'll still want to see your code to prove it.

Message 8 of 9
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you know nathand i am pretty in a situation since i was payed to develop this product and so im not the owner of the code and for this i cant share it, from the other side i spent some of my time (it is not expensive, but not free as well) dealing with "calibration" of NI hardware. So right now i prefer to close this topic and shut up. hope you dont mind too much

thank you

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