FPGA target to host DMA transfer speed

[michaeljoseph]

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@nathand wrote:

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@michaeljoseph wrote:

We (my advisors and I) think that the summing pairs approach would preserve more information than simply throwing away every other point. Also, we can avoid overflow because each 16-bit number only contains 12-bits of actual information. The 16-bit number will just need to be divided by 16 before summing because the 12-bits of information are placed in the 12 MSBs of the 16-bit number. Does that sound right?

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Depends on what the code is actually doing, but generally if you convert a 12-bit value to 16 bits, the useful bits are stored in the low 12 bits so that the value remains constant. No division by 16 should be necessary.

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The NI 5772 manual says that the 12 bits in the 16 bit number are left justified (foot note on page 16, http://www.ni.com/pdf/manuals/373625a.pdf). I assumed that left justified means that the 12 bits are moved over so that they occupy the 12 MSBs. That's where I got the idea of dividing by 16 before adding the numbers. Does that sound right? It seems to be working, but I could be missing something.

[nathand]

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@michaeljoseph wrote:

The NI 5772 manual says that the 12 bits in the 16 bit number are left justified (foot note on page 16, http://www.ni.com/pdf/manuals/373625a.pdf). I assumed that left justified means that the 12 bits are moved over so that they occupy the 12 MSBs. That's where I got the idea of dividing by 16 before adding the numbers. Does that sound right? It seems to be working, but I could be missing something.

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Seems like you have it right, sorry for the confusion. I haven't worked with a 5772, and I haven't seen many other analog input devices set up that way, but there's probably some advantage such as avoiding the logic needed for sign extension.