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FPGA resource efficiency questions

Hello,
 
I am using the PXI-7811R.  I have a large state machine running inside a Single Cycle Timed Loop (SCTL).  I have some questions about some of the labview functions:
 
1) Index Array - If I want to pull out a fixed set of bits (or even just one bit) from a variable (wire), is this the most efficient way to do it?  Is it essentially just a wiring operation consuming no logic (for wired constants)?
 
2) Less than Zero - The help says the logic is proportional to the width of the variable.  Would it just be better to pull off the sign bit (MSB) of the signed integer, if it is set then the number is less than zero?  This should be free - it would just be a wiring operation, no?
 
3) I have a FXP 35 bit signed result (+/-,35,35) from subtracting two FXP 34 bit signed numbers.  I am squeezing the result into a signed 14 bits (this becomes part of a U32 later for passing through a DMA FIFO, all bits are used).  I have an overflow indicator that goes true if the subtraction result requires more than 13+1 bits (13 data, 1 sign).  In the attached image, I have two ways of doing this:  comparing if the result is greater than 8191 or less than -8192, or (less intuitively) splitting the array into the data bits (least significant 13 bits, d12 to d0) and everything else.  For the result to not have overflowed, the bits d34 through d13 must either be 0 (for a positive result) or 1 (for a negative result since it is two-compliment).  I then build the 14 bit result using the original sign bit and the original data bits, and include the overflow flag.  Since the number to bool and split array functions are free, really to check the overflow I am just NANDing and ORing 21 bits.  Any ideas if this is more efficient than comparing two 35 bit numbers, or would the compiler optimize this out?
 
4) Is the Increment function more efficient than adding by 1, or does it optimize to the same thing?
 
I wish the saturation functions supported FXPs Smiley Sad   I think it would have made my life simpler!
 
Thanks for you opinions!
 
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Sorry, added image file.....
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tartan5,
  1. Index array is not just a wiring operation.  See this topic in the LabVIEW help on Array Palette details.  The only other way I could think of doing this would be to use the array subset VI, but the output of this is an array and must be handled as such.  However, the index array function seems to work slightly better in terms of logic:


  2. Again, pulling off the MSB is not free as it consumes logic in proportion to the array size.  However, so do the comparison VIs.  Roughly, they compile to the same thing unless you want to compare by a power of two:


  3. You can use saturation with the fixed point data type.  Just right-click and select properties on the function to select this.  At the lower level, enabling saturation is not much different than what you are doing as it performs a full comparison.  See this help document on using the fixed point data type for more information on this.
  4. Adding one and incrementing compile to roughly the same thing:

Regards,

Craig D
Applications Engineer
National Instruments



Message Edited by Craig D on 11-19-2007 10:50 AM
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One thing I think I should clarify is how logic is used with the index array function.  If you wire a constant to the index terminal, logic will only be created for this single "address".  If you wire a control to the index terminal, logic will be created for each available value that index could have.
 
 
Regards,
 
Craig D
Applications Engineer
National Instruments


Message Edited by Craig D on 11-19-2007 12:19 PM
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Hello Craig,
 
Sorry for the late response, I was off of this project for a bit but now I'm back........
 
I see that Index Array is not free, even from with a SCTL.  However, Split 1D Array should be, as per "This function consumes no logic resources on the FPGA because it is purely a wiring operation.".  Perhaps your examples were not with a SCTL, hence the high Slice count?
 
From the documentation, I was under the impression that Index array is always implemented like a for loop, hence why it's Resources field says "This function consumes logic resources in proportion to the size of the array."
 
So, I do use index array to get the sign bit, but I think it would be much better to Split the array at the MSB (to return a 1D array of only 1 element).  I'm not really looking at the value, just packing it with the rest of my data.  If I needed the discreet value, I could then "Array to Cluter" (Free, pure wiring) and then unbundle (Also Free), which then gives me a boolean.
 
As for the Saturation functions, the helps says "Specifies an input that is an 8-, 16-, 32-, or 64-bit signed or unsigned integer."  In fact, if I wire my +/- 34 bit FXP to it, I see type coercion dots, so I assume it must be coercing it to a signed 64 bit input, which would be a huge waste of resources, no? 
 
Thanks!
Howard
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Hi Howard,

I have tested the method you have described, and yes, the FPGA logic utilization is very low.  Within a single cycle timed loop, I got about 3 slices of usage.  The reason why split array does not take any logic space is due to the fact that it keeps the original array intact, and rather just references a different portion of it based on where you would like to "split" the array.  So essentially you are not really splitting it per se, but rather just referencing a different portion.  In contrast, the index array does use an interative process to find the particular index location, then actually allocates memory space for what is indexed. 

Regarding the saturation, you should use a convert to 32 bit Unsigned VI before you wire it in to your saturation functions to save more space.  This should help in optimizing the space requirements.

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