10-08-2007 11:04 AM
10-08-2007 11:07 AM
11-19-2007 10:48 AM - edited 11-19-2007 10:50 AM
Regards,
Craig D
Applications Engineer
National Instruments
11-19-2007 12:19 PM - edited 11-19-2007 12:19 PM
02-07-2008 09:46 PM
02-11-2008 10:03 AM
Hi Howard,
I have tested the method you have described, and yes, the FPGA logic utilization is very low. Within a single cycle timed loop, I got about 3 slices of usage. The reason why split array does not take any logic space is due to the fact that it keeps the original array intact, and rather just references a different portion of it based on where you would like to "split" the array. So essentially you are not really splitting it per se, but rather just referencing a different portion. In contrast, the index array does use an interative process to find the particular index location, then actually allocates memory space for what is indexed.
Regarding the saturation, you should use a convert to 32 bit Unsigned VI before you wire it in to your saturation functions to save more space. This should help in optimizing the space requirements.