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FPGA realtime

I am going to control a Hydraulic actuator, which connected with a LVDT. The LVDT gives dada 0.1 second interval but my simulation model run 0.001 time step. My simulation model is connected to hardware system (Actuator system) through a (cRIO) I am using LabView &.1. Due to mismatch of this of hardware data and simulation data some delay or error may occur how this type of prob can be handle.    
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