I have FPGA R/W nodes in 2 different cRIO RT timed loops. The idea was to segregate high speed (1ms) FPGA access from a lower speed 10ms loop. The 1ms loop has 1 FXP write and 2 I32 reads, the 10ms loop has a mix of about a dozen controls and indicators including 2 16 byte U8 arrays. Surprisingly I am not seeing an improvement in loop speed between this version and the previous version were all the FPGA access was in the 1ms loop. I would like to better understand how data is being transfered to and from the FPGA. Is there a dedicated DMA channel for this? How are multiple FPGA R/W nodes serialized? Are asynchronous operations guarenteed to be atomic? I read somewhere that any transfer over 32 bits is not atomic, but is this a problem if my 2 loops never have R/W variables that are accessed in both loops? Thanks very much.
