FPGA project best practices

[sjacksonPA]

Hi, so I currently have a project that includes a Host VI and the FPGA VI. My project is expanding though. We're adding more digital and analog signals to the project (we're adding a new C-series module to read from). This will require updates to the FPGA, and then updates to the Host VI. We'll still need the original Host and FPGA VIs though for testing of the smaller system.

My question is then what the recommended way or best practice here would be. Should I create Host_2.vi and FPGA_2.vi (or something like that) within the project. Or should I just create a new project? Thanks!

[JensG69]

IMHO that's totally up to you. Both ideas are valid and might be useful, that's totally up to you. If you do no create a new project then I recommend to at least define a new RT-target with the extended setup. But that is all.

You could also start with Source Code Control like Git, and then create a new branch.

Regards, Jens

[sjacksonPA]

Thanks, Jens!

That makes sense, I was wondering if a new target would be the way to go. If I add a second RT-target under the project though (with all the modules and an new FPGA vi), it won't cause any issues with the existing target and FPGA.vi...as long as I name things uniquely, right?

[Terry_ALE]

Hard to tell with little info but I am not sure which is best.

How different will the two be?

Do you mind maintaining them so that the old one works as well as the new one?  A good question to ask is "how will things function or be in a few months or say a year?"  This helps shake out decisions which seem ambiguous in the near term.

The more you can share with us (not just code), the better we can help out here on the forum.

[crossrulz]

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@sjacksonPA wrote:

That makes sense, I was wondering if a new target would be the way to go. If I add a second RT-target under the project though (with all the modules and an new FPGA vi), it won't cause any issues with the existing target and FPGA.vi...as long as I name things uniquely, right?

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If you make a new top level host VI and FPGA VI (with unique names),  you should not have any issues.  I have had issues trying to support the exact same code on two different targets (VxWorks based cRIO and a Linux RT cRIO).  But you should be able to keep all of your subVIs the same in both targets.