FPGA optimalisation help pls

[charlie87]

Hello, I am a new player in LV and FPGA programming. I have implemented a project but the FPGA usage is too high over 150 per cent. I have read a lot about optimalisation but I think I always do something significantly wrong. Please check my code and tell me where where the dog lies buried. I attached only a few VI.

[charlie87]

sorry..some VI a would like you to check

[nathand]

You're still missing the amplifier subVI, and is "SignalPreprocessing" the top-level VI?  If so, do you intend to run it only once?  It would be easier if you include your entire project as a zip archive.

The first thing I see is that you could make better use of single-cycle timed loops.  Replace the for loops with single-cycle timed loops, and remove the inner timed loops.  Add a little bit of logic to make the single-cycle loop act like a for loop (one comparison for the stop condition, use index array instead of auto-indexing).  See if that helps.  Also, I would use the standard math functions unless you have a specific reason to use the high-throughput versions.  Also, do you need all the feedback nodes?

[okubik]

Hello Charlie,
I can recommend you to go through CompactRIO Developer's Guide. I think it is the best way how to start for people who are not familiar with cRIO and FPGA development. You can trust me if I am telling you that you can find there more than basics

[dan_u]

Be careful with the data types. With FXP representation you have to be careful about the configuration of each FXP number.

• In your Derivation VI you subtract two FXP <+-,64,11> numbers (range -1024..1024, increment 1.11e-16), but the difference is represented as <+-,16,2> (range -2..2, increment 6.1e-5). That doesn't seem to make sense. Any math operation on 64 bit numbers will be very heavy on an FPGA.
• Also in the Derivation VI, the multiplier outputs a <+-,33,19> number, but this is coerced to <+-,64,19>...
• The signals wired to the Derivation VI are <+-,33,11> but the controls in the SubVI are <+-,64,11>, adding 31 bits.
• In your Integration VI you want to divide a value by 2. You do this by multiplying the value with 0.5. A simple bit shift (or "Scale by power of 2" with -1 wired to n) will have the same result, but will consume no resources.

[charlie87]

Hello guis, 

thanks for your answers. Yesterday I was unable to upload whole my project for bad Internet connection and today it is not always possible.

My project is here: http://leteckaposta.cz/270346853

to dan_u : thank you for comment. I have some problem with understanding FXP math.

As you mentioned there was a mistake with FXP 64/11 ( I thought I had repaired it before ).

to nathand : I do not understand the idea about making SCTL acting like for loop. Do you have some example ?

                      I thought that Hight Throuthput math is better then standard numeric math. If not please explain.

      I need feedback node to store previous value to make derivation and integration where I need to now the difference. I do not know better way how to do it. Do you ?

I will try to think about all your ideas and try to find more about it with uncle google. Then I gonna try to repaire and ask again if necessary.

If you can chack whole project..especially Filtering and Preprocessing part and If you think something else is wrong, please tell me.  

[nathand · Accepted solution]

Please upload the project, as a zip file, directly to this forum.  I, at least, will not download files from unknown foreign sites.

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charlie87 wrote:

to nathand : I do not understand the idea about making SCTL acting like for loop. Do you have some example ?

                      I thought that Hight Throuthput math is better then standard numeric math. If not please explain.

      I need feedback node to store previous value to make derivation and integration where I need to now the difference. I do not know better way how to do it. Do you ?

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The feedback nodes are fine for that purpose, I was just trying to understand whether the need for them was mathematical or if you were trying to use them for some sort of pipelining.

The high throughput math is not necessarily better than the standard numeric math.  Please see the help for "Using the High Throughput Math Functions."  From that document: "National Instruments recommends that you use the LabVIEW Numeric functions unless you need the benefits that the High Throughput Math functions provide."

Here's how you can implement a for loop as a single-cycle timed loop.  This won't compile on my machine, though - you need to resolve the issues with excessively-wide fixed-point values first, as dan_u noted.

[charlie87]

thank you very much. You all help me more than you can imagine 🙂 As I said I am a new player in FPGA and exploring new things every day 😄 😄 😄 

[charlie87]

However, I have one more question about the SCTL used instead of for loop in the shown case.

Could you explain the role of shift register in the sample ? 

[nathand]

Can you provide a link to where you found that recommendation?  I think you may be taking it somewhat out of context.  In any case, the array operations are difficult to avoid there.