I am doing RT and FPGA project. I have problems to control I/O pin direction by "FPGA method node" in FPGA VI file. (Hardware isPXIe-7820R). Problem is that I have bidirectional signals, user can set whether polarity is Input or Output and FPGA GPIO pin should be quicky configured after change. At one moment, signal works in one mode (output or input) and is electrically protected against unwanted situation.
I have normal While loop in FPGA code, where I use other stuff (registers, flat sequence, local variables, ...) and everything works. Until I add here 10x Method nodes "Set Output Enable". Some of operations are not eligible for "blue" single cycle loop, so then I use "slower" normal While loop.
I studied https://zone.ni.com/reference/en-XX/help/371599P-01/lvfpga/io_method_node/ , but there is not strictly given how realize cyclical call.
Before starting compilation and run, VI file looks good "no broken arrow". After a while of compiling it (step 2 or step 3) "Code generation error")
And piece of code is here..
(Cluster of bits contains info about required polarity to be set. Then Cluster is unbundled to bits that are used to control Enable signal in FPGA block.)
Please do you have some hint how to do it correctly ?
Hello, Dr. Freeman,
I read your issue a couple of times, and tried to understand the error you're getting.
It seems the problems comes from using your set output enable methods inside and outside single-cycled timed loops, which LabVIEW doesn't support.
Knowing that, let me try to understand what is required:
You have a cluster of boolean values defined by the user which you are using to set the output enabled methods of your DIO lines.
A good way of doing this could be having 2 separate loops, one where you update the cluster and another where you use the new cluster to set the output enabled methods.
Let me know if this solves your issue. Otherwise, we can try and think about another solution.