FPGA interloop communication for arrays

[falkpl]

I am using LV2009 and I am trying to have a producer consumer architecture where the producer is generating an array of U8 [8] data every 1microsecond in a singel cycle timed loop.  I wand to pass this data for furthur processing to a consumer loop.  I looked at the RT FIFO but no write arrays are allowed.  What are my options?  I want the data passing to not slow down this single cycle loop (40MHZ timed)

-Convert to U64 and write

-Write to control and read local?

-Implement my own fifo

I am relativly new to this sort of hw sync data passing.

Thanks for any input.

[Christian Mergl]

Hi,

I'm wondering what is the purpose of this architecture, or why creating an array, maybe we find another solution for what you want to build.

The possibilities you have to exchange data between loops in a single FPGA VI are a local, a memory block or VI or target scoped FIFO, they all have in common that they don't support array datatypes, just sclar.

When using a control with a local an array indicator will be created on the frontpanel. An Array control/indicator on an FPGA frontpanel will be implemented in FFs and also needs another copy (synchronization registers, ..) which will also be implemented in FFs. As they are limited, using a local with an Array indicator would be the worst choice.

Anyhow you can use all three methods (memory, local, FIFO) in quite the same way when you index the array using a for loop to transfer the scalar U8 elements, one after another, to the other loop. Since you create the array in a STCL you might need to use piplining then, so spliting up the code in shorter paths to get them done in one clock-cycle.

Hope this helps,

Christian