FPGA data mismatch

[sidpen]

Hi

I am trying to send a data packet of 9 bytes to a stepper motor driver over FPGA on a cRIO 9066. The first VI I used was built entirely on the FPGA and I successfully sent the data. When I moved the data array to the host/computer and kept just the I/O on the FPGA, it insists there is a data mismatch. Why is this? I would really like to be able to send the data from the host as it changes based on what I am trying to get the motor to do or read from the onboard encoder. 

[GerdW]

Hi sidpen,

which kind of "data mismatch" is worrying you?

On the RT side array size is handled dynamically, while the FPGA insists on fixed-sized arrays. Probably you get a coercion dot because of this "conversion" to fixed-sized…