12-03-2021 03:14 AM
Hello,
please can you help me understand and solve Error 61052 during FPGA compilation ?
In https://zone.ni.com/reference/en-XX/help/371599P-01/lvfpgahelp/fpga_error_codes_codegen/ the description is weak "HDL code generation error occurred. "
I do examples to learn with PXI (RT) and PXI-78xx FPGA module. On PXI, I have control screen with one bit read and one bit write example.
In RT program I use access to FPGA thru VI FPGA reference. (copied from example)
In FPGA program I use "blue" FPGA loop, where I use controls and indicators, then I do physical pin read, write thru FPGA NODE I/O.
In future I will consider changing VI FPGA Reference access, to RT-FPGA FIFO. But now for simplicity,no.
These VI files are part of BIG project. So i tried to run only these two VI files, one on RT and second on FPGA. RT cannot run, it says "FPGA not compiled". And FPGA says during compilation this error.
Thanks you for hints,
KP
12-03-2021 11:45 AM
Can you compile the examples for your hardware? This confirms your configuration is correct.
How different is your code that has the compile issue as compared with any of the examples?
The compile error you are getting is rarely solved directly. We try to figure out what is contributing to its cause by adding/removing functions and running compile tests.
How long does the compile take to fail?
12-06-2021 02:18 AM
Thanks for answering
note, variables "SW LED control" and "ID PINs" are used in RT VI file, that uses block "read/write control" to change them.
K.
@Terry_ALE wrote:
Can you compile the examples for your hardware? This confirms your configuration is correct.
How different is your code that has the compile issue as compared with any of the examples?
The compile error you are getting is rarely solved directly. We try to figure out what is contributing to its cause by adding/removing functions and running compile tests.
How long does the compile take to fail?