FPGA and RT reading encoder

[EyalZ]

Hello!
I'm trying to read the pulses of an encoder (16 pulses per turn) on the FPGA and with a pid controller in RT control the position.
The problem is that I'm loosing a lot of pulses and by that I can't get the real location, the motor speed is 30,000 RPM (no load) with a reducer of 275:1.
I tried to implement the pid in the FPGA but it didn't compile.
I saw suggestions about using DMA FIFO to send info from the FPGA to RT but I'm not sure how to use it, I only need to read the last value.
Also after a lot of changing and testing it doesn't allow me to exacute with error:
"The specified FPGA VI must be compiled in order to be used from the FPGA Interface". Although I did compiled the FPGA, so I don't understand why it shows that error..
I'm uploading the VI, using chassis cRIO-9076, NI-9403 digital module, NI-9264 module.
Thanks for your help!! 

[Michael_Munroe]

You did not include the LabVIEW project, so it is unclear how the project has been configured.  Regardless, there is still one giant bug in your architecture.  For the encoder to work in the FPGA, the two XOR gates that monitor the encoder inputs should be monitored at the fasted rate possible, (i.e. 40 MHz).  When a single transition is detected a single count is added or subtracted to the position.  The count is unchanged if no transition.

Your code has a 125us delay inside this loop where the position is calculated and sent to the FIFO.  These have to be in separate loops.  Monitor the inputs at 40MHz in one loop and then use the delay to feed the current position into the FIFO in another loop.

You might be able to eliminate the compiler warning by configuring the Open FPGA Reference with the compiled bit file instead of the VI name.