FPGA and Host vis synchronization

[LW42]

Hello,

The project attached doesn’t work properly. More specifically, when I run the kk_host_1.vi for the first time the pump works fine, meaning that the DO1 channel opens and closes successfully. However, when I push the stop button it takes at least 4 to 5 seconds to stop. In addition, when I start again the host vi, and turn on the “pump” control the open vi reference stick for at least 10 seconds before open the channel. It seems that it’s a synchronization problem however adding a delay in the kk_host_1.vi didn’t help. It’s the first time I am using FPGA mode and I think that I am missing something important. I would greatly appreciate some help.

Best regards   

[Pcorcs]

Thorfano,

After reviewing the attache project, I have a few comments regarding the code:

1. The Host VI on your PC opens 2 references to the same FPGA bitfile. Opening individual references for FPGA read-write control is not necessary to interact with the items llisted on the FPGA front panel. 

2. Thought the Open FPGA reference is configured to 'Run the FPGA VI.' The FPGA Close reference is currently configured to Reset the FPGA VI, it does not abort execution. I would reccomend for increased system response, to employ invoke methods for the FPGA VI, i.e. invoke run at the begining of host execution and invoke abort at the end of execution. Montioring the FPGA front panel, while not reccomended in deployment, will give a better indication on how the host references are interacting. In addition, the LabVIEW help documents the various settings for the FPGA close reference, please note that this function does not inherently abort the FPGA VI. 

3. From a torubleshooting standpoint, you may consider first independently testing the FPGA VI for the function you desire. As I perviously stated, working directly with the FPGA VI front panel will allow you to test the I/O, and verify that your hardware programming is correct. 

I would reccomend accessing the LabVIEW Example Finder for pre-built examples of cRIO FPGA projects. These host-FPGA examples should offer insight on configuring your host communications for more supervisory control.Remember, host interaction on your PC is subject to network communications, and will have a delayed system response. Likely, the 10 seconds delay time you are experiencing is with respect to the FPGA VI reference deployment and Reset process being called over the network.

Thank you for your time.

[Pcorcs]

Also,

You may find this link of interest:

 
FPGA Design, Development and Programming Tutorial
http://zone.ni.com/devzone/cda/tut/p/id/3358

Cheers!

[LW42]

Hello Pcorcs,

Thank you for your time and suggestions. Although I followed your advice I am still encountering problems but I need more time to evaluate their origin. In case of being able to specify more the situation I will come back.

Best regards