FPGA - Why use Express VIs in Singly Cylce Time Loop

[Matt_AM]

Hey Fancy Folk,

TL;DR, does the SCTL really offer that much of an advantage for express VIs that take 100's of cycles to output data?

Background:

I just finished up the self paced FPGA training.  I have a question regarding the Single Cycle Time Loop (SCTL) and express Vis. I understand that the SCTL offer a tremendous speed advantage to your code since the loop executes in a single cycle.  However, what I couldn't wrap my head around was why someone would want to use the SCTL with an express VI that would take 100's of cycles before the input data would be ready to process.  In the online training, the instructor used the FFT express vi for their example.  I don't have exact numbers on me, but I think it took 64 cycles to be able to read new data and it took 1000 cycles to output unique data once it was read.

Question:

Does something like the FFT really gain that much of an advantage in the SCTL? Chaining multiple 100's of cycles express Vis (such as windowing and scaling to go with the FFT) would cause additional delays. I feel like all the delay between when a new input is given to when the data is processed and output takes away from the main benefit of SCTL, which is speed.

Thanks,

Matt

[Terry_ALE]

SCTL is must have for high throughput designs.

Complex functions such as divide, square root, log, trig functions, FFT, FIR, need more than one cycle.  With FPGAs you need to look at throughput, latency, utilization, and clock speed to name a few.  With pipelining (it's a setting) you get full throughput rate of the SCTL clock.  That is, after you pay the latency price.

For example.  LabVIEW 2018 on a 7976, a 64 sized FFT can be set to run in an SCTL, 1 cycle per input throughput with latency of 179 cycles.  That means the first value will take 179 cycles to come out but after that assuming you keep data flowing in, you will get valid values on each clock cycle.

I suggest going back to a project and making a new VI, open up the FFT and play around with the settings to see the above.

What application are you looking to build using LabVIEW FPGA?

[Matt_AM]

Terry_ALE,

Thanks for getting back to me.  As of now, I am not really planning on designing with an FPGA.  With the free online training due to COVID and slower than normal workload, I was looking into the RT and FPGA training.  I figured now would be a great time to learn about what else LabVIEW can do.

The main test my group runs which has an FPGA at the heart of the design is a torque ripple test, where the FPGA monitors and outputs a waveform to an electronic load which outputs a very clean waveform to the motor.  This is a old tester and one day something that I would love to update (hardware and software, it was designed in like LV 7.1 with hardware equally as old).

Is it safe to assume that "speed is inversely proportional to latency" for FPGAs?  By this I mean that if I want higher speeds I am sacrificing my latency (how long the new data takes to become a valid output) and if I want a lower latency I am sacrificing my speed. 

Another thing that I didn't understand during the training was the Express VI sections, and since it was online, I couldn't exactly ask a teacher said clarification questions. Would you have any good resources to learn about using multistage express VIs in SCTL?  I had trouble understanding how I was supposed to properly use the Express VIs with a "ready for input" of multiple cycles while updating the SCTL with current data. 

In the training they did an FFT that took 64 cycles before it could accept new data and I couldnt wrap my head around how that would actually function.  Since Analog In can't be in a SCTL since it takes multiple clock cycles, I assume you'd have a seperate loop read an analog in and send it to a FIFO.  Then in the SCTL, use the express VI to determine when to read the FIFO based on the ready for input wire to go T.  My general assumption was the FIFO would get into an overflow situation if the Express VI took too many clock cycles to be ready for a new input. 

Sorry I'm moving the goal posts on ya with my original question, I am just trying to wrap my head around the concepts from that section.

Thanks,

Matt