FPGA VI Optimization

[LawrenceD]

I am working on a project utilizing a cRIO 9035 and a full set of c series modules however my FPGA VI is right at the edge of using all of the LUTs available and so most times it will fail to compile with an estimated 103% of LUT usage. I  do not feel that the vi is so complex that it actually should be using that much of the resources so my thought was that my code having been built using modified versions of a couple of the example programs was just inefficient and after reading all of the white papers and tutorials that I could find on optimizing FPGA code I was not making any headway.

The purpose of the project is to run 6 9503 stepper drivers along with a 9401 DIO module, and one 9215 analog module (I believe I can run this one outside the FPGA but the code has not been added in any case). I have included a zipped copy of the project and the FPGA Vi in question is right there at the front. If anyone could make suggestions on how I might be able to cut down on resource usage I would be much appreciative.

Thanks,

Larry D

[Muri777]

I cant open the file because you have a newer version of LabVIEW to me (im using 2015) but if youre sure youve done it all correctly, I do know that if you compile your FPGA again you will yield different results. Not sure on the exact % but if you try compiling it a few times you might get under the threshold. Just a thought!

[LawrenceD]

Thanks for the reply, I do not know that I have done everything that could be done to optimize the program. I have tried for a couple of days to get a good compile and the only time I got a good compile it decided it had to recompile it despite no changes to the FPGA VI.

[Intaris]

If you can save back to 2015 I can have a look also.

[LawrenceD]

I am going to be away from my Development Computer for the rest of the week but once I get back I will back save it.

[MaxJoseph]

It would be great if you could post images of key parts of the code too, for those of us who do not access to an install of labview (me!)

Generally you can do a few things to reduce the number of LUTs that your design uses. Check out page 59 of the user guide to see some hints:

Reduce the bit depth you use where possible

Be aware of FXP bit depth increasing as a result of some operations

Avoid arrays

Use SCTLs

[Mx.Y]

Hello Lawrence,

I'm encountering exactly the same problem with a 9114 and just one module 9503. I'm trying to run the example "Multiple Axis". Have you found a solution ? I'm interested,

Thanks,

Margaux

[SaileshK]

Hey Mx.Y,

I'd also recommend creating a new thread for your issue and reference this thread in that one. That is just so it can get more visibility and we can hopefully work towards a solution!