I am using a PXI-7831R board and I have set aside a block of onboard memory, which I write to several times during execution of the FPGA program. After everything is finished running, I would like to read this block of memory directly from the Host VI using a Memory Read. When I attempt to read this memory however, I get an array of all 0's. I have monitored all the values I store in memory throughout execution, and they are all valid and what I expect. I know that all the values are being stored correctly; the funny thing is that when I stop execution, and then start it back up, the previous value is still in memory. The problem seems to be occurring in the Memory Read function on my host VI.
Do you have a suggestion or explanation? Does calling Memory Read from the Host VI work normally, or does the fact that it is running on the host system alter or impair functionality?
Thanks a lot for the help.
Solved! Go to Solution.
You cannot access your targets memory directly from the Host VI. You will have to read from the memory in another loop on the FPGA (preferably another loop) and write that to a dma FIFO for communication directly to the Host Interface like previously described. Basically writing to the DMA fifo is like writing to the memory, except in the memory case you have addresses that you can individually access and the DMA is a fifo (first in first out) so you can't access individual pieces of information out of order.
Here is a great tutorial on it.
I just stumbled upon the same problem. Only thing is that I am using a sbRIO. So OK, I have to use a FIFO to access FPGA Memory. We'll see when compiling is finished...
But why is it then possible to drag a memory item from project explorer and drop it to a host VI? Is ist then allocating twice the memory? In my eyes, the purpose of having a memory item in project explorer is accessing it from different VIs. This is not easy to understand for someone who is a newbie in FPGA programming.
I'm using LV 8.6.1. Is the behaviour different in newer versions?
You are correct, the purpose of having a memory item in the project explorer is so that it can be accessed from multiple VIs. With FPGA Memory items, the same FPGA memory block can be accessed from multiple VIs, but the VIs have to both be FPGA VIs running on the same FPGA. The FPGA memory is physical memory within the FPGA, so only FPGA VIs can access it at run time.
With the FPGA DMA FIFOs, the data communication is one direction for each FIFO, passing data either from FPGA to Host Memory, or from Host to FPGA Memory. DMA FIFOs are a useful method for passing large amounts of data between host and FPGA target.
This behavior of DMA FIFOs and FPGA Memory is consisent in all versions of LabVIEW FPGA.
Unfortunately, LabVIEW doesn't warn users of the error if they accidentally drag an FPGA memory item onto their RT block diagram.
For more information on FPGA Memory, or other data transfer & storage mechanisms within LabVIEW FPGA, I recommend consulting the LabVIEW FPGA help. Here is the topic on FPGA memory: http://zone.ni.com/reference/en-XX/help/371599F-01/lvfpgahelp/creating_memory_blocks/
I absolutely agree with Spex. I was a little vague in my post because I knew that the application was just trying to transfer data from the FPGA VI to a Host VI. In that case you would use a DMA FIFO to transfer data, not an FPGA Memory read (which is impossible). If you wanted to store data in memory and read it in a dfferent section of your FPGA code (a subVI) then you can with another Memory read (you cannot use a DMA FIFO to read FPGA memory).
The last case, and I think this might directly relate is if you want to store data into memory on the FPGA and then want to later transfer that data to the Host VI. In that case you would read the Data on the FPGA read memory method, then write that data to a DMA FIFO to then be read back out on the Host VI.
The DMA FIFO is just a tunnel to transport data from the FPGA VI to the Host VI or vice versa.
Thank you for clarification, Spex and Andrew.
The thing is that I implemented a pretrigger function continuously sampling an input in order to be able to record some time before and after a trigger event. I don't see a way to do this directly with a FIFO. My idea was that maybe Memory is kind of like a dual port RAM accessible from FPGA and host. This way I simply would have passed two pointers to the host to display data directly from memory. But when i realised this being not true, I implemented the FIFO, which is meanwhile working. The only thing is that this seems overly complicated for what I'm actually doing.
A tiny little bit more background information in context help could also have been helpful besides LV preventing the user from putting the memory item in a host VI.