FPGA: Timed Loop vs. Loop Timer?

[JKSH]

Hello,

I'd like to create an FPGA loop that runs at a fixed rate. Does it matter whether I use a Timed Loop structure, or a Loop Timer express VI in a regular while loop? Under what circumstances would I choose one over the other?

I understand that the Loop Timer approach can cause the code in the loop to execute twice before timing is established (but that's not an issue for me here). Are there any other differences in the two approaches?

Thanks in advance.

[ABCPrograms]

Start here.  It's a document about Compact RIO and FPGA.  They will explain when to use different timed loops

[JKSH]

Hi Bjorn,

For the FPGA, that guide demonstrates the use of Single-Cycle Timed Loops for high-performance code, and demonstrates the use Loop Timers for controlling data acquisition rates. But, my question was about differences between using "multi-cycle" Timed Loops and the Loop Timer express VI.

The only difference I've found is this: Code parallel to the Loop Timer will execute twice at startup without a wait in between, but code in a Timed Loop will always be timed correctly even at startup. So my question is: is there any other differences between the two? I've found none so far and I don't think there's any, but I'd like to double-check.

[CMal · Accepted solution]

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@JKSH wrote:

But, my question was about differences between using "multi-cycle" Timed Loops and the Loop Timer express VI.

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In an FPGA targeted VI, all timed loops are single cycle timed loops (SCTL).  This means all code within a SCTL must execute in one clock cyle, so there are some types of nodes that cannot be used in such a loop.  In a regular while loop with a timer, you can use a wider variety of functionality, but the loop will typically run much slower.

These documents may be helpful in learning how to use timed loops on FPGA:

Using Single-Cycle Time Loops to Optimize FPGA VIs

Optimizing your LabVIEW FPGA VIs: Parallel Execution and Pipelining