FPGA Loop Time with Mean DC

[Peter_Bham]

I am using a DC Mean (express VI) in parallel with an RMS (express VI).  The Mean is set for 50 Samples. 

What is the loop rate and how long to acquire the 50 samples?  Is the loop timer required (800 Ticks at 40MHz)?

[tobriant]

Hello Peter,

So from my understanding, if you're sampling at 40MHz, you'll be pulling in a sample every 2.5e-8 seconds.  This means you'll get to 50 samples after 1.25us (1.25e-6).  

I believe you'd need to set your while loop rate to the however many ticks needed to wait 25ns.

If you're gathering a single sample from these VIs every loop, I would check to see if you've gone through 50 loop iterations with an Equal? VI and have that boolean wired up to the stop terminal.  Alternatively, you can just use a for loop with 50 iterations.  Each loop will allow you to auto-index an output array.