LabVIEW
FPGA LOOP RATE
shiva@adi wrote:
i have attached snip of 10ms loop, where previous iteration duration value is 7 or 8. What does 'previous iteration duration' mean? why it shows 7 or 8 ,when i set it to 10ms?
Previous Iteration Duration is the time taken to do the tasks inside the loop, for the previous iteration. It is not the time between the previous iteration and the current iteration.
shiva@adi wrote:
on a particular day the actual loop iteration duration is around 20ms but it is set to 10ms. after RT restarted, iteration duration is within 10ms. what may cause the delay?
You have a wait function in your loop. Remove it! The "Timed Loop" is meant to control the loop speed. By implementing the "Wait until next ms multiple" node, you instruct the structure to take longer. This also explains your 10, 20 ms iteration times. It will wait, and then miss the target timing!
shiva@adi wrote:
what is discard missed periods and maintain original phase.
Discard missed periods instructs the loop to skip over iterations that were supposed to happen at a previous time. Maintain original phase tells it to remain in sync with the expected timing. More details can be found here: Configuring Timed Loops
Without seeing the subVI, it's impossible to say what might take time in your loop, but I'd expect if you remove the wait everything should be fine (provided the subVI executes quickly).
shiva@adi wrote:
In the subvi I'm adding previous iteration calculated value to current value. If 'discard missed period' is checked and loop rate is exceeded set time. Does it add current value or continue with previous value?
Sorry - I don't understand what this means. Please attach the subVI, and perhaps before you do that, consider if using Clusters would allow you to tidy/simplify your block diagram. If you prefer, attach both the VI and the nested VI (subVI) and I can demonstrate what I mean regarding clusters.
