FPGA Improve Code to Fit In Single Cycle Timed Loop

JScherer · ‎07-29-2021

Hello All,

I have the following code below in a single cycle timed loop and I need to get the timing down by about 5 1.2ns. If anyone has suggestions, it would be appreciated.

My inputs are all U16 and can range from 0 to u16 max.

The output determines if the input coordinates x, y are inside the ellipse defined by h, k, a, and b

Edit: the error is by 1.2 ns

Terry_ALE · ‎07-29-2021

First I'd look at pipelining: https://zone.ni.com/reference/en-XX/help/371599P-01/lvfpgaconcepts/fpga_pipelining/

Then I'd look at high throughput math: https://zone.ni.com/reference/en-XX/help/371599P-01/lvfpga/ht_math_pal/

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FPGA Improve Code to Fit In Single Cycle Timed Loop

FPGA Improve Code to Fit In Single Cycle Timed Loop

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