FPGA - IP Block Enable Signal

[JussiJii]

Hello all,

I have created a IP Integration Node from a VHDL Ip block. Originally I had DFF registers without enable signal and FPGA didn't compile after I added enable to registers. After that I got this problem that when I compile and synth. my VHDL block, the compiler gives an error that "formal enable has no actual or default value". Is there some setup where I can drive enable port or do I have to use some spefici LabVIEW block? It seems that inserting boolean value directly to the port doesn't solve the issue.

[aevans1]

Hi JussiJii

Could you upload your vi to see exactly what you're doing

Thanks

[JussiJii]

Hi,

sorry I haven't updated this. I found the solution and the cause of the problem was LabVIEW fpga project files. I had previously made CLIP component from my VHDL block.When I made IP integration node from the same file, LabVIEW somehow tried to use files from CLIP node which caused then some really wierd problems. I was using updated VHDL block with some signals removed. Labview probably tried to fiend connections to those not existing signals from CLIP node and that generated previously mentioned error. Which actually makes sense because the port wasn't driven by anything. Wierd thing was that even that I used updated component in VI design, labview used somehow clip node which has some ports what integrate node hadn't. Anyway, it took a while to figure out the problem.