I'm attempting to synchronize AI (9223) and AO (9262) on an FPGA using the User-Controlled I/O Sampling palette, and I'm getting my I/O Write Status Method reporting a "Sample Gated".
I go to the help and it says: "Sample Gated returns TRUE when the Generate I/O Sample Pulse Method function generates a sample pulse that is gated." (Thanks for the helpful tip!)
So my first set of questions are:
My second set of questions revolves around trying to understand causes and avoid this condition. According to the help, a sample pulse can be gated for the following reasons:
My third set of questions involves how this actually works...
My fourth set of questions revolves around NI documentation:
My fifth set of questions revolves around your experience:
Thanks in advance for your insights!
These are all good questions. I attached a couple of presentations that explain the internal workings of the User Controlled I/O Sampling nodes and how they communicate with the modules.
These help show how to run at full speed, and explain what causes Sample Gated, Timeout, and other errors to occur.
Based on the 9262 timing waveforms, it looks like the sample rate is 1MS/s divided by the number of channels being written. So if you are writing to two channels, the max sample rate is 500 kS/s per channel, correct?
How is the LV FPGA to 9262 module DB15 configured? Is it a parallel bus able to carry parallel samples for all 6 channels or does one sample tie up the entire bus for ~1 us?
If it is 1 MS/s per channel, how do you interleave the separate writes? Are there separate write node signal lines - one for each of the Write I/O nodes? I guess I still have no idea how the interface bus works between the FPGA and 9262 module.
The 9262 can update all the channels in parallel at 1 MS/s.
To achieve this rate in LV FPGA:
When the I/O Write Node runs, it will transfer data for all channels to the module in parallel allowing you to update all channels at 1 MS/s.