FPGA: How can I ensure that I may use the same vi in RT across projects when the FPGA design changes but the FPGA indicators/controls which the vi accesses don't change?

[AnthonV]

Thanks Nathan, even though I like to see the glass half full, the two downsides I can see for this typedef'd method you mention is:

1) when the FPGA interface changes (e.g. an addition of a indicator, FIFO etc.), the owner of the init.vi in the image above would have to recompile the vi,

2) It would be impossible to use the same init.vi for different FPGA designs, and this is a big issue when init.vi is part of a class and thus has to have a fixed set of terminals for all inherited versions.

I'm hoping to try both methods out soon and report back.