FPGA Host Timing Vision Assistant

[lafuan]

Hi

Im working on thesis with title comparasion of image processing between fpga and microcomputer using myRIO and Raspberry Pi. The result i got is Raspi is faster than the myRIO. Why is that? i use tick count to calculate processing time in Host VI and OpenCV python. The myRIO is should be faster right? Is there anything wrong in my code? can someone take a look at it? thanks

nb: I know that Vision Assistant use SCTL to compile. but how to calculate the processing time?

[elcalverado]

Hi lafuan,

In your host code, it looks like you are benchmarking the time it takes for the entire while loop to run once. In that loop, you are opening a connection to the FPGA bitfile, downloading and running it, then transferring the image to the FPGA for processing before passing it back. Opening a connection to the FPGA, loading, and running the bitfile are initialization operations and can take a good amount of time, so are you sure you want to include that in the benchmark time? 

What are you actually looking to compare to the the RaspPi? If you are only looking to see how fast the FPGA is able to process an image, you should perform the benchmarking in the FPGA VI itself.

I don't see anything wrong with your actual Vision code. Btw, what are you running on the Raspberry Pi?

-Jordan

[lafuan]

Ohh i see, i didn't know that connection to FPGA take a good amount of time. And i think to exclude that in my benchamarking code

I am looking for process time in RaspPi. How can you do that ini FPGA VI? The FPGA VI itself use Single Clock Timed Loop to perform the block diagram and use 1 cycle clock or 25 nanoseconds every process. I can't use that

I am running OpenCV in my RaspPi

Thanks for your answer, it's been a great help!!!

[elcalverado]

If you are using a single-cycle timed loop in the FPGA, then every loop iteration will take 1 clock cycle. But the FPGA vision VIs do their processing over several loops as valid data being read from the FIFOs becomes available. So it isn't true that all the image processing will occur within 25 nanoseconds.

On an IC-3173 that I have, I put in some additional benchmarking code to see how long all of the different components of your host VI were taking. For my system, which will most likely be different than what you would see with a myRIO, I get the following:

• Entire VI to run: 1067 ms
• Time to send image to FPGA, process it, and send it back: 71 ms

So you can see that the majority of the time is spent doing everything other than actual image processing. 

-Jordan

[lafuan]

What benchmarking code did you use? can i see your code?

Thank You

[elcalverado]

Here you go. Added benchmarking between different sections of code. Something to note: DMA Retrieve time (ms) includes both the time it takes to do the image processing and send the image back to the host over the DMA FIFO.

-Jordan